JPS58151053A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an IC in small area which can be driven at a high speed with a low power consumption by connecting in common the sources of Schottky junction gate type MESFETs to a current source and by connecting two output terminals of the circuits providing loads to the drain to the gates of a pair of MESFETs cascade- connected respectively. CONSTITUTION:The sources of MESFETs Q21, Q22 are connected in common and also connected to a current source 26, FETs Q23 and Q24 are cascade-connected, and a buffer power supply voltage is supplied 27 to the source of FETQ24. When a signal of the terminal 24 is ''H'' level, FETQ24 is ON and therefore an output terminal rapidly becomes ''L'' level. When the terminal 24 is ''L'' level, the ON current of FETQ23 is supplied and thereby a load connected to the terminal 25 is rapidly charged and becomes ''H'' level. Since the FETs Q23 and Q24 turn ON and OFF complementarily, a power is little supplied even when a low impedance capacitive load is connected to the terminal 25 under the steady state and only a current increases during the transient time in the switching condition. Accordingly, a capacitive load can be driven with a low power consumption. Moreover, since an ON current of the FETs Q23, Q24 becomes a load drive current, the width of gate of the FETs Q23, Q24 can be narrowed and occupied area of circuit can also be narrowed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device of a Schottky junction gate field effect transistor (hereinafter referred to as MESFET) circuit, particularly when connecting the output of a current switching type logic circuit to a low input impedance logic circuit. The present invention relates to a semiconductor integrated circuit device that reduces the area occupied by the circuit and also reduces the propagation delay time.

First, to describe this type of technology, Fig. 1 shows a circuit in which an output buffer using a source follower is connected to a current switching circuit.
1 is a ground terminal, 12 is a source power terminal, 13 is a reference voltage terminal, 14 is a signal input terminal, and 16 is an output terminal.

The sources of MESFET Ql 1 pQ,2 are commonly connected, and the drain of MESFET Q13 is connected to ground. Resistors R11, R12, and R13 are respectively MES FET Ql 1 + Ql21 Ql 3
This is the load. Further, a current source 16 is connected between the common source terminal of MESFETs Qll and Ql2 and the source power supply terminal 12.

In this circuit, when the signal input terminal 14 is set to rHJ level, MESFETQll turns ON, MESFETQ
12 is turned off (OFF), and the output of the output terminal 15 becomes rLJ level. On the other hand, connect the signal input terminal 14 to rLJ
level, MESFET Qll is OF F,
MESFET Ql2 is turned ON, and the inverted output of the signal input terminal 14 is obtained from the output terminal 15.

In this case, the output impedance seen from the output terminal 15 corresponds to 1/9 m of MESFET Q13 in terms of a small signal, but in terms of large amplitude operation, the current sweeping ability to the output terminal 16 is equivalent to the ON of MESFET Q13. This is the difference between the current and the current flowing through the resistor R13, and the ability to draw current from the output terminal 16 is determined simply by the resistor R13, with no contribution from the MESFET Q13.

Therefore, in order to obtain a large current sweeping ability, the resistor R13
All you have to do is make it bigger. However, in this case, the current drawing ability will deteriorate because the resistor R13 is large. Therefore, the resistor R13 is a large capacitive low impedance load that is designed so that the current sweeping ability and the current drawing ability are almost equal. When connecting to output terminal 15, increase the gate width of MESFETQ13 and connect resistor R1.
3 needs to be made smaller.

As a result, MESFETQ13. The current flowing through the resistor R13 increases, and power consumption increases. Furthermore, MESF
As the gate width of ET Ql 3 increases, the area occupied by the circuit increases.

The present invention was made in view of the above-mentioned drawbacks, and its purpose is to
An object of the present invention is to provide a semiconductor integrated circuit device which can be driven at high speed with low power consumption and can reduce the area occupied by the circuit.

Embodiments of a semiconductor integrated circuit device according to the present invention will be described below with reference to the drawings. FIG. 2 is a circuit showing one embodiment of the present invention. 21 is the ground terminal.

22 is a Goosumi source terminal, 23 is a reference voltage terminal, 24 is a signal input terminal, and 26 is an output terminal.

The source terminals of the MESFETs Q21 and yQ22 are commonly connected, and a current source 26 is placed between the common connection terminal and the source power supply terminal 22. The source terminal of MESFETQ23 and the drain terminal of MESFETQ24 are commonly connected, and a buffer power supply voltage is applied from terminal 27.

Now, if the signal input terminal 24 is set to rHJ level, ME
SFET Q21 is ON9MESFETQ22 is 0FF
Therefore, voltages at rLJ and rHJ levels are applied to the gates of MESFETQ23 and Q24, and the MES
FETQ23rQ24 is turned off and turned on, respectively.

Therefore, the output of the output terminal 26 is at the rLJ level. In this case, a large amount of current is drawn from the output terminal 25 by the ON current of the MESFETQ24, so that the potential of the output terminal 25 can rapidly reach the rLJ level.

On the other hand, when the signal input terminal 24 is set to "L" level, the 5FET Q21. Q22 is OFF, respectively.

ONL and MESFETQ23tQ24 are each ON.

Since it is turned off, the output terminal 26 becomes "H" level. At this time, MESFETQ23 is connected to the output terminal 25.
Since the on-state current is swept out, the load connected to the output terminal 26 is rapidly charged, and the potential rises to the rHJ level. In this way, MESFETs Q23 and Q24 are turned on and off in a complementary manner, so the current consumption in steady state is:
If the current source 26 is removed, only the current flows through the output terminal 25, and when a capacitive load is connected to the output terminal 26, the current is almost equal to zero. Therefore, the current consumption is
It only increases in a transient state during switching, and as a result, a capacitive load can be driven with low power consumption. Furthermore, in this circuit, MESFETQ23. Since the on-current of Q24 directly becomes the load driving current, the gate width of the MESFET can be reduced, and the area occupied by the circuit can be reduced.

It should be noted that the present invention is not limited to the above embodiment, but can be applied to the MESFET Q23. of FIG. By switching the connections to each gate terminal of Q24, the signal input terminal 24
The logic of the output terminal 26 can be changed. As shown in FIG. 3 showing another embodiment of the present invention, a diode D31 is connected between the ground terminal 31 and the MESFET Q32.
By inserting tD32'D33, the rHJ level torque applied to the gate terminal of MESFETQ34 is reduced, and the MES
A circuit that prevents gate deterioration of F'ETQ34 can also be obtained. In addition, in Fig. 3, the diode D31 #D3
2' Although three CDs 33 are used, the number is not limited to three, and the source power terminal 32. Of course, it may be changed depending on each power supply voltage of the power supply terminal 3A.

As described above, the semiconductor integrated circuit device of the present invention can drive a low impedance load at high speed with low power consumption, and further reduces the area occupied by the circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional semiconductor integrated circuit device, FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 3 is a circuit diagram of a semiconductor integrated circuit device according to another embodiment of the present invention. It is a circuit diagram. 11.21.31... Ground terminal, 12, 22
゜27.32,3 completed・・・・・・Power terminal, 23.33
...Reference voltage terminal, 14, 24.34...
...Signal input terminal, 15, 25.35... Output terminal, 16°26, 36-@H---Current source 1Q11
1Q12eQ13IQ211Q22・Q23・Q24・
Q31・Q32・Q33・Q34°゛°°°. Schottky junction gate field effect transistor/R
111R12tR13IR21gR22IR311R3
2゜・・・Resistance. Name of agent: Patent attorney Toshio Nakao and one other person II
Figure I No. 3111

Claims (1)

[Claims] 1st. a current switching circuit in which a current source is connected to a common source terminal formed by connecting the source terminals of second Schottky junction gate type field effect transistors in common, and a load is connected to the drain terminal of each of the field effect transistors; 2 of the transistor cascade connection circuit in which the two sets of output terminals are commonly connected to the source terminal of the third Schottky junction gate field effect transistor and the drain terminal of the fourth Schottky junction gate field effect transistor. What is claimed is: 1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is connected to two gate terminals.