JPS5815076B2 - time measuring device - Google Patents

Description

[Detailed description of the invention] To count clock pulses during the desired time.

Therefore, digital measurement of time can be performed.

However, since there is a limit to the operating speed of the counter, in order to accurately measure minute time, it is necessary to extend the time to be measured by a known magnification.

For this purpose, a device is used that integrates a constant input during the time to be measured, then increases the integral constant by a known multiplying factor, performs inverse integration, and calculates the inverse integration time until the output returns to its original level.

However, when two or more minute measured times arrive in succession, each measured time must be processed by a separate integrator, which causes errors due to the inconsistency in the characteristics of each integrator. In order to prevent this, a constant temperature bath or the like would be required, which would require an enormous size of equipment.

The present invention provides an apparatus that is free from such drawbacks and is capable of accurately measuring each of a plurality of consecutively arriving minute times.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing operating waveforms of the portions indicated by the same reference numerals as in FIG.

That is, the measured time 11.1, such as a, is applied to the terminal T.
Two rectangular wave inputs p and q having a time width of 2 and arranged in series in time are added.

The first integrator 11 integrates the output of the constant voltage source E1 each time the rectangular wave input is applied, and is reset each time the input disappears.

Therefore, the first integrator 11 sends out an output as shown in Figure 2, but the changeover switch S1 first sends this output to the holding circuit H1.
Add to.

When the first signal p disappears, the switch is switched by the second signal.

Therefore, the holding circuit H1 delivers the output shown in FIG. 2C, which is applied as one input to the comparator C via the changeover switch S2.

In addition, the controller applies the signal k to the second integrator 2 and starts it at the same time that the first rectangular wave in the input signal a disappears, so that the integrator integrates the output of the constant voltage source E2. Starting, an output as shown in FIG. 2e is applied to comparator C.

Since the comparator C is also activated by the above signal and applies the signal f in FIG. 2 to the gate circuit G, the gate circuit G is opened and the output pulse train g of the clock pulse generator 0 is counted by the counter N. .

Next, the signal e applied from the second integrator 2 to the comparator C
The level of the output signal C of the holding circuit H1 gradually increases.
When the level vl is exceeded, the output signal f of the comparator C disappears, the gate circuit G is closed, and the counting operation of the counter N is stopped.

The counted value of this counter N is applied to the register R1 via the changeover switch S3, and is recorded in the register.

At the same time, the signal k applied from the controller K to the second integrator 2 and the comparator C disappears, the second integrator is reset, and the operation of the comparator C is also stopped.

Furthermore, as mentioned above, when the first signal p whose time width is to be measured disappears, the switch S1 is switched by the signal, so the second signal q causes the holding circuit H2 to switch the first integrator ■1. An output obtained by integrating the output of the constant voltage source E1 is stored.

Therefore, this holding circuit H2 sends out an output as shown in FIG. d is applied to comparator C.

At the same time, a reset signal j is applied from the controller K to the counter N, and the switch S3 is switched by the signal ■.

Furthermore, after a suitable short time r, the signal k is sent out again, and the second integrator 2 and the comparator C are activated.

Therefore, a signal is sent from the comparator C as shown in FIG. 2f, the gate circuit G is opened, and the counter N starts counting the clock pulse train g.

Furthermore, since the second integrator 2 integrates the output of the constant voltage source E2, when its output e gradually increases and exceeds the output level 2 of the holding circuit H2, the output signal f of the comparator C disappears. Gate circuit G is closed.

The output signal of the counter N is sent to the register R via the switch S3.
2, the count value at that time is recorded in the register.

Further, when the signal 1 disappears together with the second input signal q and the switch S1 is restored, and the output signal f of the comparator C disappears, the signals i and I disappear and the switches S2 and 83 are also restored.

Furthermore, the disappearance of the signal resets the second integrator (2), the comparator C stops operating, and the counter N is also reset by the signal j, so that the device is completely restored to the state before activation.

By the above-described operation, digital quantities corresponding to the time widths of the rectangular waves P and Q in FIG. 2f are recorded in the registers R1 and R2.

The time width of the rectangular waves P and Q is proportional to the level Vl s V2, and this level V1+■2 is the input signal p of the terminal T.
, q is proportional to the time widths t1 and t2, so the digital amount indicates the time widths t1 and t2.

By appropriately selecting the ratio of the constant voltage source E1°R2 and the integration constants of the first integrator (1) and the second integrator (2), the time widths of the rectangular waves P and Q can be set to 1 of the signals p and q, respectively.
It can be multiplied by 00 times or 1000 times.

Therefore, when the period of the clock pulse is constant, the time width of 1. , 12 can be precisely measured.

In addition, since the output of the first integrator is stored in the holding circuit and compared with the output of the second integrator, measurement is possible even when the signals p and q are very close to each other, and the allowable time interval is the same as that of the first integrator. Only the integrator reset time.

Moreover, since the same first integrator and second integrator are shared for each signal p, q, etc., there is no risk of errors occurring between the measured values of their time widths.

Although the above actual case describes the case of measuring the time width of two signals p and q, it is also possible to measure the time width by increasing the number of holding circuits even when a large number of signals arrive in succession. It can be done.

Further, the circuit for holding the integral value by the last signal is omitted, and the constant voltage source E1 and the first integrator 1 are disconnected at the same time as the last signal disappears, and the reset timing of the integrator is further delayed. The integrator itself can also be used as a holding circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.
3 is a time chart illustrating the operation of the device shown in the figure. In the figure, T is an input terminal of a signal whose time width is to be measured, K is a controller, El and R2 are constant voltage sources, 1.
■2 is the first and second integrator, Hl. R2 is a holding circuit, C is a comparator, 0 is a clock pulse generator, G is a gate circuit, N is a counter, and R1 and R2 are registers.

Claims (1)

[Claims] 1. A first integrator that integrates constant inputs during each of the measured time periods arranged in series in time and is reset when each measured time period ends; one or more integral output holding circuits each storing a value integrated by the integrator; a second integrator that integrates a constant input a plurality of times and is reset at each end of each integral operation; and the second integrator. one comparator to which the output of the one or more holding circuits is applied as one input and the output of the one or more holding circuits is sequentially applied to the other input and sends out a signal when they become equal; and the second integrator. The gate circuit is comprised of a gate circuit that is opened each time integration is started and closed each time the comparator sends out a signal, and a counter that counts clock pulses that are applied during each opening period of the gate circuit. Characteristic time measurement device.