JPS58150198A - System for checking memory - Google Patents

Abstract

PURPOSE:To judge the normality and abnormality of a memory having plural memory elements arranged in a matrix-like configuration, by making an arrangement that the memory is dividing into several groups and checking at every group to complete checking even of a memory having a large capacity in a short time. CONSTITUTION:The output of an FF group 5 is made effective by controlling an FF8 and data are written in an FF corresponding to a designated memory group, and then, data are simultaneously written in and read from memory elements 11-48 in parallel. Try-state gates 3-1-3-8 are controlled by a read signal outputted as the result of AND and the output of AND gates 2-1-2-8 obtained by AND operation are read out to a data bus as data to be inspected. Moreover, try-state gates 4-1-4-8 are controlled by a read signal outputted as the result of OR and the output of OR gates subjected to OR operation are read out. Then data to be inspected are judged by comparing them with expected value data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory checking method for determining the normality/abnormality of a memory having a plurality of memory elements arranged in a matrix, and is particularly applicable to large capacity memory. The present invention relates to a memory checking method suitable for diagnosing memory in a short time.

[Prior art and problems]

FIG. 1 is a block diagram illustrating a conventional memory checking method. In the figure, 11, 12. ~IM
．． 21, 22. , to 2M. Nl, N2, to N
M is a memory element arranged in a matrix, for example RA
M (random ● access ● memory) element, which includes memory elements l1 to IM. 21 to 2M, · song ·, constitutes a memory element row of Nl to NMHM bits, memory element 11.21, ...... NIU bit 0, memory element 12, 22, ... ...N2Fi bit 1, memory element IM. 2M. ......NM corresponds to pitch M-1. Note that the horizontal direction of the same bits and the vertical direction indicate the address direction. For memory elements arranged in this manner, the conventional memory checking method is as follows.

The microprogram first writes data to each address in the memory, then reads it, and compares the corresponding Q data with the expected value data.The operation is repeated to determine whether the memory is normal or abnormal. .

However, such conventional memory checking methods have a drawback in that as memory capacity increases, a very long time is required for checking.

[Purpose of the invention]

The present invention is a memory checking method for determining the normality/abnormality of a memory having a plurality of memory elements arranged in a matrix. The purpose of the present invention is to provide a memory check method that can complete the check in a short time even if the memory is small.

[Structure of the invention]

To achieve the above object, the memory checking method of the present invention is a memory checking method for determining the normality/abnormality of a memory having a plurality of memory elements arranged in a matrix. in parallel
,? The parallel read data is subjected to AND operations and OR operations for each bit of one word, and the results of the AND operation and OR operation are used as the data to be inspected. The present invention is characterized in that it determines whether the memory is normal or abnormal by comparing it with expected value data.

[Embodiments of the invention]

FIG. 2 is a block diagram showing an embodiment of the hardware configuration according to the present invention, and FIG. 3 is a flow chart explaining the present invention. FIG. 4 is a diagram for explaining the memory determination method using the board data of the present invention. In FIG.
Gates 3-1 to 3-8 and 4-1 to 4-8 are tristate 1 gates, 5 is a flip-flop group, 6 is a decoder, 7-11 to 7-14 are NOR gates, and 8 is a flip-flop. Flop, 11 to mallet are memory elements, *C3
ll to *C3y4 indicate chip select signals. The entire memory device is divided into g groups consisting of memory groups 1 to f.

Each memory group is constructed in the same manner as memory group 1. Hereinafter, looking at memory group 1, memory group 1 has memory elements 11 to 11 arranged in a matrix of 4 rows and 8 columns, and each memory element has 1 memory element.
For example, it is of 64KXl bits, and the memory number is 11.
The memory elements 21 to 18 constitute a 64K x 8 bit memory element row, and similarly, the memory elements 21 to 28, and 31 to 38
．． The memory element rows consisting of 41 to 8 bits are also 64K x 8 bits. Note that this horizontal direction is the bit direction,
The vertical direction indicates the address direction. Chip select signal*
CS 11 is supplied to each memory chip select terminal of memory elements 11-18, and similarly chip select signal *C812ilt memory elements 21-28. The chip select signal *C813 is supplied to each chip select terminal of the memory elements 31 to 38, and the chip select signal *C814Fi is supplied to each chip select terminal of the memory elements 41 to 41. Then, when the chip select signal *CS 11 becomes a logic 0 level, each of the memory elements 11 to 18 becomes readable/writable 11IIK. The same applies to other chip 0 select signals. The read data of memory indexes 11 to 41 corresponding to bit OK is OR.
input to gate 1-1 and AND gate 2-1,
The read data of the memory elements 12 to C corresponding to bit 1 is sent to the OR gate l-2 and the AND gate 2-2.
The read data from memory element 18 corresponding to bit 7 is input to OR gates 1-8 and AND gates.
The signal is input to gate 2-8. These configurations are the same for the other memory groups 2 to g. The output of OR gate 1-1 is connected to the data bus pin through tristate gate 4-1. The output of AND gate 2-1 is tristate gate 3-1
to bit 0 of the data bus. Similarly, the output of %OR gate l-2 is connected to bit 1 of the data bus through tristate gate 4-2, and the output of AND gate 2-2 is connected to bit 1 of the data bus through tristate gate 3-2. The outputs of the OR gates 1-8 are connected to bit 1 of the data bus.
8 to bit 7 of the data Φ bus, and the output of AND gates 2-8 is connected to tri-state gates 3-8.
is connected to bit 7 of the data bus via n. Tri-state gates 3-1 to 3-8 are controlled by AND result read signals, and tri-state gates 4-1 to 3-8 are controlled by AND result read signals.
1 to 4-8 are controlled by the OR result read signal.

Flip 70 knob group 5 is the step select signal *C
It has 7 lip-flops, the number of which corresponds to S11 to C3g4 (4Xy), and is controlled by the MPU of the main unit via the data bus, and the output of each of the 7 lip-flops is connected to the output of the chip. The selection signal is supplied to one input terminal of the NOAH games 7-11 to 7-14. The decoder 6 decodes the upper digits of the memory address signal, and its output is supplied to the other input terminals of the NOR gates 7-11 to 7-1I4. Chip/
Select signal * CS 11 is the output of the NOR game) 7-11. Either the flip-flop corresponding to the gate 7-11 is selected and becomes a logic level, or the output of the decoder 6 is the NOAR game) 7-11. When the output corresponding to becomes a logic level, the chip select signal rate C3lI becomes a logic θ level. Below, the chip select signal books C812 to *C814 also have a 17 lip, a slip corresponding to 70 knob group 5, a 70 knob opening, an output terminal corresponding to decoder 6, and a corresponding NOR gate. There it is.

The same is true for the chip select signal s c s ii. Slip flop 8 is 7 rip, 70 rip #
It is used together with I5 when executing the memory check of the present invention, and when data is written to the clip-flop 8 when executing the memory check, the output of the 7-lip-flop group 5 is enabled, and the output of the decoder 6 is enabled. The chip select signal of the memory group to be checked using the 7-lip flop #P5 is controlled to be at logic 0 level.

In the device constructed as described above, the procedure of the memory according to the present invention according to the Cheno-Yuen style will be explained in accordance with the 70-ken chart of FIG. First, the %7 lip-flop 8 is controlled to make the output of the 7-lip flop group 5 valid, and the output of the decoder 6 is invalidated, and then the next process is performed.

■ Of the slip-flop group 5, the specified memory
Write data to the clip-flop corresponding to the group (for example 1) and send the chip select signal (*C811
to *C814) to the logical θ level to designate memory group (1).

■ Specify the memory address.

■ Data can be transferred simultaneously to memory elements 11 and 11 in parallel.
Write.

■ Simultaneously read data from memory elements 11 and 11 in parallel.

■ Tri-state game) 3-1 to 3 based on the AND result read signal for the parallel fist read data
-8, and reads out the AND gates 2-1 to 2-8's output data to the data bus as the data to be tested, and uses the OR result read signal to control the AND gate 4-1. The outputs of the OR gates 3-1 to 3-8, which have been subjected to the logical sum operation, are read out to the data bus as data to be inspected.

Compare the test data with the expected value data to determine whether the memory is normal or abnormal.0 If normal, move on to ■; if abnormal, proceed to ■
Move to.

■ Perform abnormal oversalting such as replacing memory elements. ■ Determine whether or not the memory check has been completed for all memory groups.

If it is not completed, return to ■ and repeat the checks up to ■ for memory groups 2 to l in the same way.0 Therefore, as shown in Figure 2, memory group length check, = If you run the memory check by dividing it by 4, it will be 4.
Since the checks of the two memory element rows are performed simultaneously, the check of all the memories can be completed in one quarter of the time of the conventional memory check method. The longer the group leader stays together, the shorter the time required for checking.

Next, we will explain in more detail the memory determination method in Figure 3 (■) with reference to Figure 4. Assuming that the expected value data used for checking 0 memory is 0101 0101J, this data will be written to the memory element. However, in the actual read data, it is 0 (
2), in the second row and fourth column, "1" changes to "0", and t
In the third row and third column, "0" is transformed into "1". Therefore, if we perform a logical OR operation on each bit of these parallel read data, we will get the above “0” to “1” as shown in (3).
"1" appears in the bit that has changed to "1", which is different from the expected value data (1). Also, when we perform the @fill operation for each bit of these parallel read data, as shown in (4), when the above "1" is converted to "0", "0" appears in the other bit and the expected value is This will be different from data (1). As a friend, the memory becomes rOJ, r
Regardless of whether it turns out to be IJ, the abnormality performs a logical sum operation and a logical product operation.

Judgment can be made by using the results as test data and comparing the test data with expected value data.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, even if the memory has a large capacity, the memory is divided into several groups in the address direction, and the memories in the groups can be written and read all at once. .

Since it is possible to determine whether the memory is normal or abnormal, the time required for this check is much shorter than the conventional memory checking method, which determines whether the memory is normal or abnormal by writing and reading each address. It becomes shorter. In particular, when checking whether a memory is normal or abnormal, if there is an abnormality in the memory, even if it is possible to determine which memory is abnormal, the entire memory element must be replaced. Being able to confirm that the memory is healthy is a top priority. In this respect, the present invention trJ is very convenient because it can perform parallel write and parallel Φ read to collectively confirm that everything in the memory group is normal. According to the determination method of the present invention, the length of the memory group is not particularly limited, and it goes without saying that it can be selected as appropriate. Furthermore, the length of a memory group does not change the time required to check that group. Rather, the time required for the check is determined by the number of groups σ, but when compared with the conventional memory check method, the time required for the check is shorter by the length of the group, that is, the time required for the check is shorter than the length of the group. It will only take a while 0

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a conventional memory checking method, FIG. 2 is a block diagram illustrating an embodiment of a hardware configuration according to the present invention, FIG. 3 is a flow chart explaining the present invention, and FIG. The figure is a diagram illustrating a memory determination method based on board data according to the present invention. 1-1 to 1-8...or game), 2-1 to 2-
8... AND gates, 3-1 to 3-8 and 4-1 to 4-8... tristate gates, 5... flip-flop group, 6... decoder, 7-11 to 7
−． 4...Noah Gate, 8...Flip-flip, 11.12. I M, 21.22.28.2M
, 31.32, 38.41.42.48. Nl,
N2 and NM...memory elements, *C811 to *C3
g4...Chip select signal. Patent applicant: Usatsuk Electronics Industry Co., Ltd. Representative Patent Attorney: Yobu Kyotani (1 other person)■3 Zuhi 4 Ju

Claims (1)

[Claims] In a memory checking method that determines whether a memory containing multiple memory elements arranged in a matrix is normal or abnormal, the memory is divided into multiple groups in the address direction, and data is written in parallel and The parallel read data is subjected to AND and OR operations for each bit of one word, and the results of the AND and OR operations are used as the data to be inspected, and the data to be inspected is set as the expected value. A memory checking method that uses aS to determine whether the memory is normal or abnormal by comparing it with data.