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JPS58147899A - Measuring method of semiconductor memory - Google Patents

Measuring method of semiconductor memory

Info

Publication number
JPS58147899A
JPS58147899A JP57030952A JP3095282A JPS58147899A JP S58147899 A JPS58147899 A JP S58147899A JP 57030952 A JP57030952 A JP 57030952A JP 3095282 A JP3095282 A JP 3095282A JP S58147899 A JPS58147899 A JP S58147899A
Authority
JP
Japan
Prior art keywords
voltage
memory
power supply
state
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57030952A
Other languages
Japanese (ja)
Other versions
JPS6235200B2 (en
Inventor
Yoshio Watanabe
義夫 渡辺
Katsumi Kaizu
海津 勝美
Takamitsu Jinno
陣野 孝光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57030952A priority Critical patent/JPS58147899A/en
Publication of JPS58147899A publication Critical patent/JPS58147899A/en
Publication of JPS6235200B2 publication Critical patent/JPS6235200B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81Threshold
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004Voltage

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To take a measurement of the threshold value of a complete LSI which is conventionally impossible by analysing the operation of a flip-flop from the inversion of a storage state caused by a temporary drop in power voltage. CONSTITUTION:A voltage VCC is lowered approximately to the threshold voltage of a driving transistor (TR) in a memory cell at xV/sec (procedure 1) and then raised to its original level again (procedure 2). Then, the stored information in the memory cell 1 is read out to check whether inversion to ''1'' is caused or not (procedure 3). The minimum value of the lowered voltage VCC is set to lower values gradually at ZmV steps and the procedures 1-3 are followed repeatedly. In the procedure 3, when the stored information is inverted to ''1'', the minimum value of the lowered VCC in the preceded procedure 1 is regarded as the critical voltage of the TR which was conducted just before the power voltage is lowered between two driving TRs in the memory cell. On the basis of this critical voltage, the threshold voltage of the TR is found.

Description

【発明の詳細な説明】 本発明は半導体メモリの完成品を対象としてメモリセル
内のトランジスタの閾値電圧を間接的に測定する方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for indirectly measuring the threshold voltage of a transistor in a memory cell in a finished semiconductor memory.

半導体メモリの完成品において、内部素子の閾値電圧の
経時変化はメモIJLSIの電気的特性劣化を引き起こ
し、ひいてはメモリLSIは正常動作をしなくなる。こ
のため、内部素子の閾値電圧を測定し、その変動を観測
することは重要なことであるが、これまで完成品のLS
Iにおいて内部素子の閾値電圧の測定は不可能とされて
いた。
In a finished semiconductor memory product, changes over time in the threshold voltages of internal elements cause deterioration of the electrical characteristics of the memory IJLSI, and as a result, the memory LSI no longer operates normally. For this reason, it is important to measure the threshold voltage of internal elements and observe its fluctuations, but until now it has not been possible to
In I, it was considered impossible to measure the threshold voltage of internal elements.

本発明は、これまで不可能とされていた完成品のLSI
における閾値電圧の測定を可能とするため、絶縁ゲート
電界効果トランジスタまたはショットキーゲート電界効
果トランジスタを用いたフリップフロップ形スタティッ
ク・ランダム・アクセス・メモリにおいて、電源電圧を
一時的に低下させることにより生じる記憶状態の反転か
ら、フリップフロップの動作解析より、メモリセル内の
2個の駆動トランジスタのうち電源電圧を下げる前に導
通状態であったトランジスタの閾値電圧を求めることを
可能とした半導体メモリの測定方法を提供するものであ
る。
The present invention provides a complete LSI, which was previously considered impossible.
In flip-flop type static random access memories using insulated gate field effect transistors or Schottky gate field effect transistors, the memory generated by temporarily lowering the supply voltage can be used to measure the threshold voltage of A method for measuring semiconductor memory that makes it possible to determine the threshold voltage of the transistor that was in a conductive state before lowering the power supply voltage among the two drive transistors in a memory cell, based on state reversal and analysis of flip-flop operation. It provides:

以下図面を用いて本発明の詳細な説明する。The present invention will be described in detail below using the drawings.

第1図は本発明を適用したスタティックNチャ/ネルM
O8RAM (Metal 0xide Semico
nductorRandom Access Memo
ry )の6−Tr型ツメモリセル示したものである。
Figure 1 shows a static N-channel/channel M to which the present invention is applied.
O8RAM (Metal Oxide Semiconductor
ndductorRandom Access Memo
ry) shows a 6-Tr type memory cell.

同図において、VCCは電源電圧を表わし、’r、 +
 T2はエン・・ンスメント形駆動トランジスタ、’r
、 + ’r、はデプレッション形負荷トランジスタを
表わす。また、’rl+ ’r2の閾値電圧をそれぞれ
Vt+  + vT2とする。例えば、V、、> V、
 ノ場合、T!を導通状態に設定した後、vccをvl
、〉vcc>vT2の関係になる値まで低下させると、
での低下途中のある電源電圧でT1は閉塞状態になり、
T2は導通状態になる。すなわち記憶状態が反転する。
In the figure, VCC represents the power supply voltage, 'r, +
T2 is an enforcement type drive transistor, 'r
, + 'r, represents a depletion type load transistor. Further, the threshold voltages of 'rl+'r2 are respectively set to Vt+ + vT2. For example, V,, > V,
If no, T! After setting vcc to vl
,〉vcc>vT2,
T1 becomes blocked at a certain power supply voltage that is in the middle of decreasing at
T2 becomes conductive. In other words, the memory state is reversed.

この状態はVCCを元の電圧に戻しても維持される。本
発明は、この現象を基になされたものである。
This state is maintained even if VCC is returned to its original voltage. The present invention is based on this phenomenon.

上記の基本的考え方を基にして本願の第1の発明の一実
施例を用いて説明する。メモリの記憶状態は1″および
′0#の状態があるが、ここでは初期に”0”の状態で
あ不と仮定して説明を行なう。
An embodiment of the first invention of the present application will be explained based on the above basic idea. Although the storage state of the memory is 1'' and '0#, the following explanation assumes that the initial state is "0".

VCCt’メモリセル内の駆動トランジスタの閾値電圧
の近くまでxV/seeで下げ(手順1)、再び元の電
圧までyV/seeで上げる(手順2)。引き続きメモ
リセルの記憶情報を読み出し、′1″に反転したか否か
を調べる(手順3)。VCCを下げる最低値をZmVス
テップで次第に低い値に設定し、手順1〜手順3を繰り
返し行なう。手順3において記憶情報が1”に反転した
場合′、直前の手順1でVCCを下げた最低値をもって
、そのメモリセルの2個の駆動トランジスタのうち電源
電圧を下げる前に導通状態であったトランジスタの臨界
電圧と呼ぶこととする。この臨界電圧を基に、そのトラ
ンジスタの閾値電圧を求めることができる。本実施例の
場合、v1□〉VT2のときの臨界電圧をVCRとすれ
ば、 vTl =vCR−%フ/ItI      (1)と
なる。ここで、IDはT3のドレイン電流、β1はT1
の利得定数を表わす。
VCCt' is lowered at xV/see to near the threshold voltage of the drive transistor in the memory cell (procedure 1), and raised again to the original voltage at yV/see (procedure 2). Subsequently, the stored information of the memory cell is read and it is checked whether it has been inverted to '1'' (procedure 3).The minimum value for lowering VCC is gradually set to a lower value in ZmV steps, and procedures 1 to 3 are repeated. If the stored information is reversed to 1'' in step 3', the transistor that was in a conductive state before lowering the power supply voltage among the two drive transistors of that memory cell is This is called the critical voltage of Based on this critical voltage, the threshold voltage of the transistor can be determined. In the case of this embodiment, if the critical voltage when v1□>VT2 is VCR, then vTl=vCR-%f/ItI (1). Here, ID is the drain current of T3, β1 is T1
represents the gain constant of

第2図の棒グラフは、上述の測定方法で、ある半導体メ
モリのすべてのメモリセルについて、各メモリセル内の
2個の駆動トランジスタのうち閾値電圧の高い側のトラ
ンジスタの臨界電圧を測定した結果を表わす相対度数分
布である。また、第2図の曲線−’(X)は該測定結果
をもとにメモリセル内の駆動トランジスタのうち閾値電
圧の低い駆動トランジスタを含む全メモリセルの駆動ト
ランジスタの臨界電圧の分布を該分布が正規分布と仮定
して求めたものである。さらに、第2図のV。ROは同
一チップ上にある製造工程検査用トランジスタの閾値電
圧の実測値から(1)式を基に求めた該検査用トランジ
スタの臨界電圧の値である。その値は分布況の平均値と
(平均値−標準偏差)との間にある。第2図に示した本
測定法の実施結果から、本測定法により該半導体メモリ
のメモリセル内の2個の駆動トランジスタのうち閾値電
圧の高い駆動トランジスタの閾値電圧を高い横変で決定
できることが証明される。
The bar graph in Figure 2 shows the results of measuring the critical voltage of the transistor with the higher threshold voltage of the two drive transistors in each memory cell for all memory cells of a certain semiconductor memory using the measurement method described above. This is the relative frequency distribution. Furthermore, the curve -'(X) in Figure 2 shows the distribution of critical voltages of the drive transistors of all memory cells, including drive transistors with low threshold voltages among the drive transistors in the memory cells, based on the measurement results. This was calculated assuming that the distribution is normal. Furthermore, V in FIG. RO is the value of the critical voltage of the test transistor on the same chip, which is determined based on equation (1) from the measured value of the threshold voltage of the transistor for test in the manufacturing process. Its value lies between the mean value of the distribution and (mean value - standard deviation). From the results of this measurement method shown in FIG. 2, it is possible to determine the threshold voltage of the drive transistor with the higher threshold voltage among the two drive transistors in the memory cell of the semiconductor memory with a high lateral variation. be proven.

上述の発明では、電源電圧を下げる前の記・層状態とし
て、メモリセルの2個の駆動トランジスタのうち閾値電
圧の高い側のトランジスタが導通状態の場合には該トラ
ンジスタの閾値電圧が測定できるが、該トランジスタが
閉塞状態にある場合には記憶状態の反転が起こらず該ト
ランジスタの閾値電圧を決定することができない。本願
の第2の発明は、記憶状態の反転が必ず起こり、確実に
閾値電圧を求める方法を提供するものである。すなわち
、あらかじめメモリセルの2個の駆動トランジスタのう
ち閾値電圧が高い側のトランジスタが導通状態になるよ
うに記憶情報の書き込みを行ない、引き続いて上記一実
施例の方法を実行すればある電圧が導通状態にある駆動
トランジスタの臨界電圧以下に相当する値の場合、必ず
記憶状態の反転が生じるので導通状態に設定した駆動ト
ランジスタの閾値電圧を必ず求めることができる。2個
の駆動トランジスタのうちどちらの駆動トランジスタの
閾値電圧が高いかを求める一方法としては、電源電圧を
零から定格値まで上げたとき、2個の駆動トランジスタ
のうち閉塞状轢にあるトランジスタの閾値電圧が他の閾
値電圧より高いことを利用する方法がある。
In the above invention, as the layer state before lowering the power supply voltage, if the transistor with the higher threshold voltage of the two drive transistors of the memory cell is in a conductive state, the threshold voltage of the transistor can be measured. , when the transistor is in a closed state, no reversal of the memory state occurs and the threshold voltage of the transistor cannot be determined. The second invention of the present application provides a method in which reversal of the memory state always occurs and the threshold voltage can be reliably determined. That is, if memory information is written in advance so that the transistor with the higher threshold voltage of the two drive transistors of the memory cell becomes conductive, and then the method of the above embodiment is executed, a certain voltage becomes conductive. If the value corresponds to the critical voltage or less of the drive transistor in the conductive state, the memory state will always be reversed, so the threshold voltage of the drive transistor set in the conductive state can always be determined. One way to find out which of the two drive transistors has a higher threshold voltage is to find out which one of the two drive transistors has a higher threshold voltage. There is a method that utilizes the fact that the threshold voltage is higher than other threshold voltages.

メモリセルの2個の駆動トランジスタのうち閾値電圧の
高い側のトランジスタの閾値電圧を半導体メモリの全メ
モリセルについて求める場合、本願の第2の発明を適用
すると半導体メモリの全メモリセルについて2個の駆動
トランジスタのうち閾値電圧の高い側のトランジスタを
導通状態にする必要があり、記憶情報の書き込みが煩雑
である。
When determining the threshold voltage of the transistor with the higher threshold voltage among the two drive transistors of the memory cell for all the memory cells of the semiconductor memory, if the second invention of the present application is applied, the two drive transistors for all the memory cells of the semiconductor memory are It is necessary to turn on the transistor with a higher threshold voltage among the drive transistors, making writing of storage information complicated.

本願の第3の発明は簡単な書き込み操作で半導体メモリ
の全メモリセルについてメモリセルの2個の駆動トラン
ジスタのうち閾値電圧の高い側のトランジスタの閾値電
圧を求めることができる方法を提供するものである。第
3図は、この第3の発明の一実施例の測定手順を示すタ
イムチャートを示したものである。まず、全メモリセル
に記憶情報゛′O″′を書き込む(手順11)。次にV
。0をメモリセル内の駆動トランジスタの閾値電圧の近
くまでxV/secで下げ(手順12)、再び元の電圧
塘でyV/ seoで上げる(手順13)。引き続き、
メモリセルの記憶情報を読み出し′1″に反転したメモ
リセルがあるか否かを全メモリセルについて調べる(手
順14)。vcoを下げる最低値をZmVステップで次
第に低い値に設定し、手順12〜手順14を繰り返し行
なう。手順14において、′1”に反転したメモリセル
がある場合、直前の手順12でVCCを下げた最低値を
もって、当該メモリセルの2個の駆動トランジスタのう
ち電源電圧を下げる前に導通状態であったトランジスタ
の臨界電圧とする。この臨界電圧を基に(1)式から該
トランジスタの閾値電圧を求める(手順15)。上述し
た手順11及び手順12〜手11iii15の繰り返し
くプロセスエ)により、確率的に約半数のメモリセルに
ついて2個の駆動トランジスタのうち閾値電圧の高い側
の閾値電圧を求めることができる。次に、すべてのメモ
リセルに記憶情報“ビを書き込み(手順16)、手順1
2゜手順13の操作にしたがってV。0を下げ、再び元
の電圧にVCCを戻す。引き続き記憶情報を読み出し、
今度は″Onに反転したメモリセルがあるか否かを調べ
る(手順17)。vccを下げる最低値をZmVステノ
グで次第に低い値に設定し、手順129手頭13゜手順
17を繰り返し行なう。手順17において @Q#Iに
反転したメモリセルがある場合、直前の手順12でV。
The third invention of the present application provides a method for determining the threshold voltage of the transistor with the higher threshold voltage among the two drive transistors of the memory cell for all memory cells of a semiconductor memory by a simple write operation. be. FIG. 3 shows a time chart showing the measurement procedure of an embodiment of the third invention. First, write memory information ``O'' to all memory cells (step 11).Next, V
. 0 is lowered at xV/sec to near the threshold voltage of the drive transistor in the memory cell (step 12), and raised again at the original voltage level at yV/seo (step 13). continuation,
The stored information of the memory cells is read out and all memory cells are checked to see if there is a memory cell inverted to '1'' (step 14).The lowest value for lowering the vco is gradually set to a lower value in ZmV steps, and steps 12 to Repeat step 14. In step 14, if there is a memory cell inverted to '1', lower the power supply voltage of the two drive transistors of the memory cell to the lowest value that VCC was lowered in the previous step 12. Let be the critical voltage of the transistor that was previously conducting. Based on this critical voltage, the threshold voltage of the transistor is determined from equation (1) (step 15). By repeating step 11 and steps 12 to 11iii15 described above, the threshold voltage of the higher threshold voltage of the two drive transistors can be found for approximately half of the memory cells with probability. Next, write the memory information "B" to all memory cells (step 16), and step 1
2゜V according to step 13. 0 and return VCC to its original voltage. Continue reading memory information,
Next, check whether there is a memory cell that is inverted to ``On'' (step 17). Set the lowest value for lowering vcc to a gradually lower value using the ZmV stenog, and repeat step 129 and step 17. Step 17 If there is an inverted memory cell in @Q#I, V in the previous step 12.

Cを下げた最低値をもって、当該メモリセルの2個の駆
動トランジスタのうち電源電圧を下げる前に導通状態で
あったトランジスタの臨界電圧とする。この臨界電圧を
基に(1)式から該トランジスタの閾値電圧を求める(
手順15)。上述した手j@16及び手順12.手順1
31手順17 、手順15の繰り返しくプロセス■)に
より、プロセス■で求めることができなかったメモリセ
ルの各メモリセルの2個の駆動トランジスタのうち閾値
電圧の高い側のトランジスタの閾値電圧を求めることが
できる。
The lowest value obtained by lowering C is taken as the critical voltage of the transistor that was in a conductive state before lowering the power supply voltage among the two drive transistors of the memory cell. Based on this critical voltage, calculate the threshold voltage of the transistor from equation (1) (
Step 15). The above-mentioned move j@16 and procedure 12. Step 1
31 Step 17, Step 15 are repeated (Step ①) to find the threshold voltage of the transistor with the higher threshold voltage among the two drive transistors of each memory cell that could not be found in Process ②. I can do it.

上述したプロセスエ、プロセス■により半導体メモリの
全メモリセルについてメモリセルの2f固の駆動トラン
ジスタのうち閾値電圧の高い側の駆動トランジスタの閾
値電圧を求めることができる。
The threshold voltage of the drive transistor on the higher threshold voltage side among the 2f drive transistors of the memory cell can be determined for all memory cells of the semiconductor memory by the above-mentioned process E and process II.

閾値電圧の変動はメモIJLSIの電気的特性劣化の原
因となる。本発明は、メモIJLsIの電気的特性劣化
の前駆動的現象を閾値電圧の変動として測定でき、メモ
IJLsIの信頼性評価に適用し得るものである。その
一実施例を第4図に示す。第4図は、一定期間加速試験
を行なった後の閾値電圧の変化緻を求め、相対度数によ
る棒グラフで示したものである。同図に示すようにメモ
IJLsIの電気的特性劣化の前駆動的現象である閾値
電圧の増加が観測される。これより、本発明は、メモI
JLSIの信頼性評価に有効なものである・ことが明ら
かである。
Fluctuations in the threshold voltage cause deterioration of the electrical characteristics of the memory IJLSI. The present invention can measure the pre-driving phenomenon of electrical characteristic deterioration of the memo IJLsI as a variation in the threshold voltage, and can be applied to reliability evaluation of the memo IJLsI. One embodiment is shown in FIG. FIG. 4 shows the change in threshold voltage after performing an accelerated test for a certain period of time, and shows it in a bar graph based on relative frequency. As shown in the figure, an increase in the threshold voltage is observed, which is a pre-driving phenomenon of deterioration of the electrical characteristics of the memory IJLsI. From this, the present invention provides Memo I
It is clear that this method is effective for evaluating the reliability of JLSI.

以上説明したように、本発明は閾値電圧の経時変化を容
易に観測することを可能とし、メモリLSIの電気的特
性劣化を前駆症状の段階で察知することを実現可能とし
たものであり、特に短チャンネルM’08LSIのポッ
トエレクトロンのLSI特性に及ぼす影響について評価
を行なう場合に、本発明の有効性が顕著である。
As explained above, the present invention makes it possible to easily observe the change in threshold voltage over time and detect the deterioration of the electrical characteristics of a memory LSI at the stage of a prodromal symptom. The effectiveness of the present invention is remarkable when evaluating the influence of pot electrons on the LSI characteristics of short channel M'08LSI.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を適用するスタティックNチャンネルM
O8RAMの6−Tr型型上モリセル回路図、第2図は
本発明の一実施例の実験結果を示す相対度数分布の棒グ
ラフと実験結果をもとにメモリセル内の駆動トランジス
タのうち閾値電圧の低い駆動トランジスタを含む全メモ
リセルの駆動トランジスタの臨界電圧の分布を該分布が
正規分布と仮定して求めた曲1IIf(、c)と同一チ
ップ上にある製造工程検査用トランジスタの閾値電圧の
実測値から(1)式を基に求めた該検査用トランジスタ
の臨界電圧VcBoを合わせ示した特性図、第3図は本
発明の一実施例の測定手順を示すタイムチャート図、第
4図は本発明を適用して求めた閾値電圧の経時変化量の
結果の一例を示す相対度数分布図である。 特許出願人  日本電信電話公社 代  理  人   白  水  常  雄外1名
Figure 1 shows a static N-channel M to which the present invention is applied.
Figure 2 is a 6-Tr type upper Mori cell circuit diagram of O8RAM, and a bar graph of the relative frequency distribution showing the experimental results of an embodiment of the present invention. Actual measurement of the threshold voltage of a transistor for manufacturing process inspection on the same chip as the curve 1IIf (, c) obtained by assuming that the critical voltage distribution of the drive transistors of all memory cells including low drive transistors is a normal distribution. A characteristic diagram that also shows the critical voltage VcBo of the test transistor determined from the value based on equation (1), FIG. 3 is a time chart diagram showing the measurement procedure of an embodiment of the present invention, and FIG. FIG. 7 is a relative frequency distribution diagram showing an example of the results of the amount of change over time of the threshold voltage obtained by applying the invention. Patent applicant: Nippon Telegraph and Telephone Public Corporation Representative: Tsune Hakusui and one other person

Claims (3)

【特許請求の範囲】[Claims] (1)絶縁ゲート電界効果トランジスタまたはショット
キーゲート電界効果トランジスタを用いた79ノグフロ
ノプ形スタテイツク・ランダム・アクセス・メモリにお
いて、電源電圧を定格値からある電圧まで下げて再び元
の電圧に戻し、該メモリの記憶状態を読み出す操作を、
前記ある電圧を変えしかも電源電圧を下げる前の該メモ
リの記憶状態を常に同じ状態に設定して繰り返し行ない
、記憶状態が電源電圧を下げる前と異なっている場合の
前記ある電圧のうちの最大値から、該メモリセル内の2
個の駆動トランジスタのうち電源電圧を下げる前に導通
状態であったトランジスタの閾値電圧を求めることを特
徴とする半導体メモリの測定方法。
(1) In a 79-nogphronop type static random access memory using an insulated gate field effect transistor or a Schottky gate field effect transistor, the power supply voltage is lowered from the rated value to a certain voltage and then returned to the original voltage. The operation to read the memory state of
The maximum value of the certain voltage when the certain voltage is changed and the storage state of the memory is always set to the same state before the power supply voltage is lowered, and the storage state is different from before the power supply voltage is lowered. , 2 in the memory cell
A method for measuring a semiconductor memory, comprising determining the threshold voltage of a transistor that was in a conductive state before lowering a power supply voltage among drive transistors.
(2)絶縁ゲート電界効果トランジスタまたは/ヨツト
キーゲート電界効果トランジスタを用いたフリップフロ
ップ形スタティック・ランダム・アクセス・メモリにお
いて、あらかじめ閾値電圧の低い側のトランジスタが閉
塞状態となり閾値電圧の高い側のトランジスタが導通状
態になるように該メモリの記憶情報を書き込んでから電
源電圧を定格値からある電圧まで下げ再び元の電圧に戻
し該メモリの記憶状態を読み出す操作を、前記ある電圧
を変えしかも電源電圧を下げる前の該メモリの記憶状態
を常に同じ状態に設定して繰り返して行ない、記憶状態
が電源電圧を下げる前と異なっている場合の前記ある電
圧のうちの最大値から、該メモリセル内の21向の駆動
トランジスタのうち電源電圧を下げる前に導通状態であ
ったトランジスタの閾値電圧を求めることを特徴とする
半導体メモリの測定方法。
(2) In a flip-flop type static random access memory using an insulated gate field effect transistor or a Yotsuki gate field effect transistor, the transistor with a lower threshold voltage is closed in advance, and the transistor with a higher threshold voltage is closed. After writing the stored information in the memory so that the voltage becomes conductive, the power supply voltage is lowered from the rated value to a certain voltage, and the voltage is returned to the original voltage, and the stored state of the memory is read. The storage state of the memory before lowering the power supply voltage is always set to the same state, and the memory state is different from before lowering the power supply voltage. A method for measuring a semiconductor memory, comprising determining the threshold voltage of a transistor that was in a conductive state before lowering a power supply voltage among drive transistors in 21 directions.
(3)絶縁ゲート電界効果トランジスタまたはンヨノト
キーゲート電界効果トランジスタを用いたフリップフロ
ップ形スタティック・ランダム・アクセス・メモリにお
いて、あらかじめ半導体メモリのすべてのメモリセルに
対して記憶情報″’O’ (tたは’1” )を書き込
んでから電源電圧を定格値からある電圧まで下げ再び元
の電圧に戻し該メモリの記憶状態を読み出す操作を、前
記ある電圧を変えしかも電源電圧を下げる前のメモリの
記憶状態を常に@On(まだはal” )に設定して繰
り返して行ない、記憶状態が′1″(または”o’ )
に反転している場合の前記ある電圧のうちの最大値から
、前記メモリセル内の2個の駆動トランジスタのうち電
源電圧を下げる前に導通状態であったトランジスタの閾
値電圧を求め、次に該メモリのすべてのメモリセルに対
して記憶情報″′l#(または”o”)を書き込んでか
ら、電源電圧を定格値から所望のある電圧まで下げ再び
元の電圧に戻し該メモリの記憶状態を読み出す操作を、
前記所望のある電圧を変えしかも電源電圧を下げる前の
該メモリの記憶状態を常に1”(または10#)に設定
して繰り返して行ない、記憶状態が0#(または’l”
)に反転している場合の前記所望のある電圧のうちの最
大値から、前記メモリセル内の2個の駆動トランジスタ
のうち電源電圧を下げる前に導通状態であったトランジ
スタの閾値電圧を求めることを特徴とする半導体メモリ
の測定方法。
(3) In a flip-flop type static random access memory using an insulated gate field effect transistor or an insulated gate field effect transistor, storage information "O" (t or '1') and then lowering the power supply voltage from the rated value to a certain voltage and returning it to the original voltage again to read the memory state of the memory. Always set the memory state to @On (still "al") and repeat, until the memory state becomes '1' (or 'o')
Determine the threshold voltage of the transistor that was in a conductive state before lowering the power supply voltage among the two drive transistors in the memory cell from the maximum value of the certain voltage when the voltage is inverted; After writing the memory information "'l#" (or "o") to all memory cells of the memory, the power supply voltage is lowered from the rated value to a desired voltage and returned to the original voltage to change the memory state of the memory. The read operation is
By changing the desired voltage and always setting the memory state of the memory to 1" (or 10#) before lowering the power supply voltage, the memory state becomes 0# (or 'l').
), from the maximum value of the desired voltages when the voltage is inverted to A method for measuring semiconductor memory characterized by:
JP57030952A 1982-02-27 1982-02-27 Measuring method of semiconductor memory Granted JPS58147899A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57030952A JPS58147899A (en) 1982-02-27 1982-02-27 Measuring method of semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57030952A JPS58147899A (en) 1982-02-27 1982-02-27 Measuring method of semiconductor memory

Publications (2)

Publication Number Publication Date
JPS58147899A true JPS58147899A (en) 1983-09-02
JPS6235200B2 JPS6235200B2 (en) 1987-07-31

Family

ID=12318012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57030952A Granted JPS58147899A (en) 1982-02-27 1982-02-27 Measuring method of semiconductor memory

Country Status (1)

Country Link
JP (1) JPS58147899A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076124A2 (en) * 1981-09-26 1983-04-06 Fujitsu Limited Method of testing IC memories
JP2006078289A (en) * 2004-09-08 2006-03-23 Fujitsu Ltd Semiconductor memory device and test method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853775A (en) * 1981-09-26 1983-03-30 Fujitsu Ltd IC memory test method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853775A (en) * 1981-09-26 1983-03-30 Fujitsu Ltd IC memory test method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0076124A2 (en) * 1981-09-26 1983-04-06 Fujitsu Limited Method of testing IC memories
JP2006078289A (en) * 2004-09-08 2006-03-23 Fujitsu Ltd Semiconductor memory device and test method thereof

Also Published As

Publication number Publication date
JPS6235200B2 (en) 1987-07-31

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