JPS58147330U - Tuner device - Google Patents
Tuner deviceInfo
- Publication number
- JPS58147330U JPS58147330U JP4558182U JP4558182U JPS58147330U JP S58147330 U JPS58147330 U JP S58147330U JP 4558182 U JP4558182 U JP 4558182U JP 4558182 U JP4558182 U JP 4558182U JP S58147330 U JPS58147330 U JP S58147330U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- tuner device
- supplied
- synchronization
- monitor receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Systems (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のチューナ装置の例を示す構成図、第２図
は本考案によるチューナ装置の一実施例を示す構成図、
第３図はその説明に供する線図である。
１はチューナ装置、１ａは出力端子、２はモニター受像
機、５は選局回路、９は映像検波回路、１０はミキサ、
１１は表示信号発生器、１２は同期分離回路、１４はＡ
ＦＣ回路、１５はアンド回路である。FIG. 1 is a block diagram showing an example of a conventional tuner device, FIG. 2 is a block diagram showing an example of a tuner device according to the present invention,
FIG. 3 is a diagram for explaining this. 1 is a tuner device, 1a is an output terminal, 2 is a monitor receiver, 5 is a channel selection circuit, 9 is a video detection circuit, 10 is a mixer,
11 is a display signal generator, 12 is a synchronization separation circuit, and 14 is A.
FC circuit 15 is an AND circuit.
Claims (1)
に同期して発生された表示信号とが重畳された信号を得
、この信号が別個に設けられたモニター受像機に供給さ
れるようになされたチューナ装置において、電源投入時
、チャンネル切換時に少なくとも上記表示信号が上記モ
ニター受像機に供給されないようにしたチューナ装置。A signal is obtained in which a video signal and a display signal generated in synchronization with a synchronization signal separated from the video signal are superimposed, and this signal is supplied to a separately provided monitor receiver. In the tuner device, at least the display signal is not supplied to the monitor receiver when power is turned on or when switching channels.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4558182U JPS58147330U (en) | 1982-03-30 | 1982-03-30 | Tuner device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4558182U JPS58147330U (en) | 1982-03-30 | 1982-03-30 | Tuner device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58147330U true JPS58147330U (en) | 1983-10-04 |
Family
ID=30056594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4558182U Pending JPS58147330U (en) | 1982-03-30 | 1982-03-30 | Tuner device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58147330U (en) |
-
1982
- 1982-03-30 JP JP4558182U patent/JPS58147330U/en active Pending
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