JPS58143617A - Logarithmic amplifying circuit - Google Patents
Logarithmic amplifying circuitInfo
- Publication number
- JPS58143617A JPS58143617A JP57025736A JP2573682A JPS58143617A JP S58143617 A JPS58143617 A JP S58143617A JP 57025736 A JP57025736 A JP 57025736A JP 2573682 A JP2573682 A JP 2573682A JP S58143617 A JPS58143617 A JP S58143617A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- output
- logarithmic
- intermediate frequency
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G7/00—Volume compression or expansion in amplifiers
- H03G7/001—Volume compression or expansion in amplifiers without controlling loop
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は受信電界強度を測定する場合に入力レベルの対
数的電圧変動に対し、出力電圧を直線的変化とすること
(二より、受信電界強度の広いレベル変動範囲を検出で
きるようにした対数増幅回路の改良に関するものである
。DETAILED DESCRIPTION OF THE INVENTION When measuring the received electric field strength, the present invention makes the output voltage change linearly in response to logarithmic voltage fluctuations in the input level (Secondly, the wide level fluctuation range of the received electric field strength is measured). This invention relates to an improvement of a logarithmic amplifier circuit that enables detection.
まず従来の対数増幅回路について説明する。第1図は回
路構成例ブロック図で、対数増幅回路は電界強度測定器
や受信機の中間周波増幅部に設ける。図中の1は中間周
波入力、2は中間周波出力、8は対数増幅出力、4〜1
1は中間周波増幅の各段で、12.18は加算器、14
は検波器である1、4〜11の各段の増幅器の出力は入
力と同相であり、その出力抵抗と12.18の加算器入
力抵抗で分割された電圧が、加算器12.18 への出
力電圧になる。加算器12.18は相互に影響が少なく
なるように緩衝増幅器を通して検波器14で包絡線検波
をすることにより対数増幅出力8を得ている。First, a conventional logarithmic amplifier circuit will be explained. FIG. 1 is a block diagram of an example of a circuit configuration, and a logarithmic amplifier circuit is provided in an intermediate frequency amplification section of a field strength measuring device or a receiver. In the figure, 1 is intermediate frequency input, 2 is intermediate frequency output, 8 is logarithmically amplified output, 4 to 1
1 is each stage of intermediate frequency amplification, 12.18 is an adder, 14
is a wave detector.The output of each stage of amplifiers 1, 4 to 11 is in phase with the input, and the voltage divided by the output resistance and the adder input resistance of 12.18 is applied to the adder 12.18. becomes the output voltage. The adders 12 and 18 obtain a logarithmically amplified output 8 by performing envelope detection with the detector 14 through a buffer amplifier so that mutual influence is reduced.
しかしこのような回路では、(1)中間周波増幅器の初
段から終段までの位相を同じにしなければならぬため、
使用する中間周波数での位相補正が複雑になる。(2)
初段から終段までの増幅利得を大きくとると発振防止の
ため緩衝増幅器のアイソレーションを大きくしなければ
ならないなどの欠点がある。However, in such a circuit, (1) the phase from the first stage to the last stage of the intermediate frequency amplifier must be the same;
Phase correction at the intermediate frequency used becomes complicated. (2)
If the amplification gain from the first stage to the final stage is large, there are drawbacks such as the need to increase the isolation of the buffer amplifier to prevent oscillation.
本発明はこれらの欠点を取除くために行ったもので、そ
の対策として中間周波で加算する代りに直流電圧の加算
を行うことによって、位相補正を容易にし発振を防止し
易くしたことが特徴で、以下さらに詳しく説明する。The present invention was developed to eliminate these drawbacks, and is characterized by the fact that instead of adding intermediate frequencies, DC voltages are added, thereby making it easier to perform phase correction and prevent oscillation. , will be explained in more detail below.
第2図は本発明を実施した対数増幅回路の構成例図で、
1〜11は第1図と共通、12−1.12−2は加算器
、14−1.14−2 は検波器、15は加算器である
。本発明においてはまず受信機や測定器の中間周波部を
この例では4〜7よりなる前増幅器群と8〜11よりな
る後増幅器群に分け、各増幅器群の各段増幅器出力電圧
の一部を各段からはゾ同位相で取出し、群毎の共通の負
荷抵抗(図示せず)で加算した後検波して、直流出力と
なった各増幅器群の対数増幅器出力を直流加算器15で
加算し、これを中間周波部の入力lに対する対数増幅器
出力8とすると同時に、後増幅器群終段11の出力を受
信機復調器への出力2とする。FIG. 2 is a diagram showing an example of the configuration of a logarithmic amplifier circuit embodying the present invention.
1 to 11 are the same as in FIG. 1, 12-1.12-2 is an adder, 14-1.14-2 is a detector, and 15 is an adder. In the present invention, first, the intermediate frequency section of a receiver or measuring instrument is divided into a front amplifier group consisting of 4 to 7 in this example and a rear amplifier group consisting of 8 to 11, and a portion of the output voltage of each stage amplifier of each amplifier group is divided. are taken out from each stage in the same phase, added by a common load resistance for each group (not shown), and then detected, and the outputs of the logarithmic amplifiers of each amplifier group, which become DC outputs, are added by a DC adder 15. This is set as the logarithmic amplifier output 8 for the input 1 of the intermediate frequency section, and at the same time, the output of the final stage 11 of the rear amplifier group is set as the output 2 to the receiver demodulator.
なお前増幅器群の4〜7各増幅器の入出力位相差はコン
デンサ等で補正し、位相差を極力小さくすることにより
、入力信号lと増幅器7の出力の位相差を極力小さくし
、その各増幅器出力は抵抗分割で加算器12−1の入力
抵抗に加えられるもので、加算器12−1の出力は検波
器14−1で包絡線検波を行い、これによって各増幅器
の対数特性の合成されたダイナミックレンジの広い11
の対数増幅器出力が得られる。後増幅器群に属する増幅
器8〜11も前増幅器群と全く同様で、各段で位相補正
を行い加算器12−2で合成された出力を検波器14−
2で検波することにより、ダイナミックレンジの広い第
2の対数増幅器出力が得られる。続いて各検波器14−
1および14−2からの直流出力を加算器15によって
合成することにより、ダイナミックレンジの広い対数増
幅器出力8が得られる。The input/output phase difference of each of the amplifiers 4 to 7 in the amplifier group is corrected using a capacitor, etc., and the phase difference between the input signal l and the output of amplifier 7 is made as small as possible by making the phase difference as small as possible. The output is added to the input resistance of adder 12-1 by resistance division, and the output of adder 12-1 is subjected to envelope detection by detector 14-1, which combines the logarithmic characteristics of each amplifier. 11 with wide dynamic range
The logarithmic amplifier output is obtained. Amplifiers 8 to 11 belonging to the rear amplifier group are also exactly the same as the front amplifier group, and phase correction is performed at each stage, and the output synthesized by the adder 12-2 is sent to the detector 14-2.
2, a second logarithmic amplifier output with a wide dynamic range can be obtained. Subsequently, each detector 14-
By combining the DC outputs from 1 and 14-2 by an adder 15, a logarithmic amplifier output 8 with a wide dynamic range is obtained.
いま第2図の各増幅器の位相差を(ゼロが理想であるが
)θとすれば、合成された振幅は次のようになる。Now, if the phase difference of each amplifier in FIG. 2 is set to θ (ideally zero), the combined amplitude will be as follows.
θが大きくなると振幅は小さくなり、対数増幅特性の直
線性が悪くなる。しかしθが大きくてもnが小さければ
上式の第2項(sin項)が無視できるので、対数増幅
特性の直線性はあまり損われない。そしてこのような特
性のものを検波した状態では前増幅器群の群内位相差と
後増幅器群の群内位相差は各検波器出力でははり同じで
あり、入力lと増幅器たとえば7どの検波出力での位相
差は検波出力に関係しない。すなわち検波器14−1゜
14−2の出力には位相項はなく、これを加算器15に
て直流合成しても14−1と14−2の振幅成分だけの
和となり、直線性の良い対数増幅出力8が得られる。さ
らに前、後増幅器群はその入力と出力との位相差が少な
く増幅利得が2分割されて少ないので、発振条件を満た
すことも少なく発振防止にも役立っている。As θ increases, the amplitude decreases, and the linearity of the logarithmic amplification characteristics worsens. However, even if θ is large, if n is small, the second term (sin term) in the above equation can be ignored, so the linearity of the logarithmic amplification characteristic is not significantly impaired. When something with such characteristics is detected, the intra-group phase difference of the front amplifier group and the intra-group phase difference of the rear amplifier group are essentially the same for each detector output, and the detected output of the input l and the amplifier, for example 7, is the same. The phase difference between is not related to the detection output. In other words, there is no phase term in the outputs of the detectors 14-1 and 14-2, and even if they are DC-combined by the adder 15, the result is a sum of only the amplitude components of 14-1 and 14-2, which has good linearity. A logarithmically amplified output of 8 is obtained. Furthermore, since the front and rear amplifier groups have a small phase difference between their inputs and outputs and have a small amplification gain which is divided into two, they are less likely to satisfy oscillation conditions and are useful in preventing oscillation.
以上詳細に説明したように本発明においては、各増幅器
群の人、出力量位相差が少ないので発振を起こし難く特
性にバラツキがなく安定である。As described in detail above, in the present invention, since the output amount phase difference between each amplifier group is small, oscillation is difficult to occur and the characteristics are stable without variation.
また各増幅器の対数増幅特性を合成させているので、ダ
イナミックレンジの広い対数増幅が行われ直線性の良い
安定な検波出力が得られるという実用上著しい効果があ
る。Furthermore, since the logarithmic amplification characteristics of each amplifier are combined, logarithmic amplification with a wide dynamic range is performed and a stable detection output with good linearity can be obtained, which is a significant practical effect.
第1図は従来の対数増幅回路の構成例図、第2図は本発
明を実施した対数増幅回路の構成例図である。
■・・・・中間周波入力、 2・・・・中間周波出力、
8・・・・対数増幅出力、
4〜11・・・・中間周波各段の増幅器、12、12−
1.12−2.13・・・・加算器、14.14−1.
14−2・・・・検波器、 15・・・・加算器。
特許出願人 国際電気株式会社
代理人 大球 学
外1名FIG. 1 is a configuration example diagram of a conventional logarithmic amplifier circuit, and FIG. 2 is a configuration example diagram of a logarithmic amplifier circuit embodying the present invention. ■・・・Intermediate frequency input, 2・・・Intermediate frequency output,
8... Logarithmic amplification output, 4-11... Intermediate frequency amplifier at each stage, 12, 12-
1.12-2.13... Adder, 14.14-1.
14-2...Detector, 15...Adder. Patent applicant Kokusai Denki Co., Ltd. agent Okyu 1 person from outside the university
Claims (1)
て多段増幅中間周波増幅回路を用い、その全段を前増幅
器群と後増幅器群(二分け、その各段増幅器出力の一部
を各段からはゾ同位相で取出し、これを各増幅器群毎に
設けた共通抵抗にて加算した後検波し、その取出された
各増幅器群の対数増幅出力を加算器にて直流加算し、こ
れを中間周波入力に対する対数出力とするように構成さ
れたことを特徴とする対数増幅回路。A multi-stage amplification intermediate frequency amplification circuit is used as a circuit to obtain a logarithmically related output for an intermediate frequency input, and all stages are divided into a front amplifier group and a rear amplifier group (a part of the output of each stage amplifier is sent from each stage). are taken out in the same phase, added together using a common resistor provided for each amplifier group, and then detected. The extracted logarithmically amplified outputs of each amplifier group are added in direct current using an adder, and this is added to the intermediate frequency signal. A logarithmic amplifier circuit configured to provide a logarithmic output with respect to an input.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57025736A JPS58143617A (en) | 1982-02-19 | 1982-02-19 | Logarithmic amplifying circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57025736A JPS58143617A (en) | 1982-02-19 | 1982-02-19 | Logarithmic amplifying circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58143617A true JPS58143617A (en) | 1983-08-26 |
JPS6254246B2 JPS6254246B2 (en) | 1987-11-13 |
Family
ID=12174097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57025736A Granted JPS58143617A (en) | 1982-02-19 | 1982-02-19 | Logarithmic amplifying circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58143617A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04228834A (en) * | 1990-12-27 | 1992-08-18 | Toyota Motor Corp | Fuel supply device of gas turbine engine |
-
1982
- 1982-02-19 JP JP57025736A patent/JPS58143617A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6254246B2 (en) | 1987-11-13 |
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