JPS58140848A - Program execution controlling system - Google Patents

Abstract

PURPOSE:To develop a program execution controlling system in a short period of time and with a low cost and to obtain a debug console of high mobility, by selecting and executing a program by a processor unit on the basis of an external indication. CONSTITUTION:A program packed to a console unit 2 is allotted with overlap of an address to a system side 1. In case the only processor unit provided to the system board 1 executes programs, an address space is controlled by an indication given from an operator to perform the switch selection for execution of program. Then the system control or console control is carried out. As a result, the operator can perform the retrieval and indication of various types of information by means of a keyboard 4 and a display circuit 5.

Description

[Detailed description of the invention] [From @Ot1 distillate fee] From this f1 Hiro! Rodatsum running control system, the body hook is equipped with only four microphones on the system side for controlling the lansole of the system.

[Episode 110 Technical Arm Length and its O Problems] Equipped with a microphone 'a 7"H'kyt, friend information II &
In the system, the '3 console unit is connected to its hardware adjustment and software, Azobag, and maintenance roundup. This console is a department store,
Also called moth or simulator.

The representative functions of the above console are listed below.

■Continuous execution and stop of system fvx Datsum ■Single step execution of system program ■System side memory and I/1 (input/output) MA, dehe Il@a (/Wr1
t* ■Trace ■Break is in India ■Search ■O program load/store to system memory By the way, the above-mentioned Punsol Uni and To rely on the ones provided by IC manufacturers, but at present) - expensive and easy to use. It's the friend I'm missing. In other words, the above-mentioned tunnel sole units are used for SO service during product development and maintenance.
, which is unnecessary for normal functions. In fact, the console is required as described above,
I! It is not cost effective to issue this information and attach it to the system.

[originating from tsom]

The present invention has been made based on the above circumstances.
The console function implemented in the console function returns the rounding of a durum to the system side address and the operator,
The only grosser unit in the system is assigned based on external instructions! By having a configuration that selects program execution, it is possible to implement the program at low cost and in a short period of time.
The purpose is to provide a department store and gaming console that can be used for IK development.

[Summary of the invention]

Is the invention a system? - The console unit is the only one installed on the board to make effective use of the nine processor units; 22. To execute these programs, the configuration is such that the address space is controlled based on instructions from the controller (return mode; selection of system!logzum or console program execution). Also, a non-maskable interrupt (Nll
[I)].

As a result, it is possible to develop at low cost and in a short period of time, and provides a highly mobile A/D/D console.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using drawings.

FIG. 1 is a block diagram showing a single-wire connection configuration of an information processing system to which the present invention is adopted.

In the figure, number 1 is a nine system with only one processor, one, and one installed. Both have one console, and both are connected via a connection cable l.
Data is communicated via this cable l. The console door 2 is connected to a keypad 4 for controlling the interface with the operator, and a display circuit 5, and data is exchanged between the system and the operator using these input/output devices as media. The key switch 4 consists of various key switches, and the 0 display circuit 5, which is used when the operator inputs information to the system, is composed of a simple device such as a lamp. Provided with rounding notices.

FIG. 2 is a block diagram showing an embodiment of an apparatus for realizing the present invention, and in detail shows the internal structure of the 11-domain and L-1 in FIG. 1. In the figure, each block having the same number as in FIG. 1 has the same function as that block in FIG. 1, and therefore will not be described in detail here. In the figure, reference numeral 11 is a nine fvs processor unit installed in system mode 1, and in the embodiment of the present invention, the US INTICL
company) sold 8-bi, Tomicro Grosse, Su80
I am using 88. Reference numeral 12 is a ROM in which the system Grodaram is stored, and the above Grosse, ? Unit 11 is each unit connected to 11-4 based on the contents of this GLODARAM.

Control line 5.13 is the above system! RAM is used as a work area by the system. 14
．． Ill is an input/output control unit that controls connected input/output devices (not shown). The above units 11, 12, 13, 1491!5 are commonly connected via a path 20.

16 is a circuit group that controls the interface between the console 22 and
l Connected to l. Further, 11°za, zs are drivers/registers/amounts provided in the round where the system connects -do I to console side=, )j.

On the other hand, 21 is a ROM in which Zorodram for control is stored, and j is a RAM.

23 is a control unit that controls the connection interface between the system side and the console side. Details of the internal circuit etc. will be described later. Reference numeral 24 is a group of function control circuits for the console, which includes a rozo circuit that realizes the original functions of the console as described in the prior art section;
It is.

zs, xi, and zv are drivers/receivers provided at the ninth position to connect the console l to the system side. IM,
19 is the key to be connected to 4, display circuit (LED)
It is an input/output control unit that controls the input/output data 44 such as 15.・The above unit j 1 e 22
# Mutual 3, 24.2g.

:19d Commonly connected to internal path 30.

Furthermore, 31. 1 and 31 are path lines through which address data or control signals are propagated, and are designated by the first EK and constitute a nine connection cable 1.

Hereinafter, the operation of the nine embodiments shown in FIG. 2 will be explained.

The processor unit 11 is connected via a path line 20 to a ROM 7'a stored in a ROM 1j mounted on the system side or a ROM JJ mounted on the console side.
Run one of the grams.

If the console units are not connected to the system (if console unit l is connected, the execution mode is system mode), Zorose, Sayuni, and To11 are stored in ROM12 and the nine system! RAM 13 and various input/output control units 1 based on the program
4 and 15 to execute , f, respectively.

If the execution mode is console mode, L Rose and Naeet 11 will be sent to BOM via Drino 4/Receiver 1 Tono Threat Twin J Todo Tsuino Ira/Regi-Δ2J.
J J K Execute the stored pununru control fa datsum.

;Nor control fwx Datsum is input/output control ay
) J a e j The display circuit IK address, data, etc. are displayed via #, and the operator operates the 9 key to instruct operations to read various input data, so the key may be -r4. The designated circle 6 functions (f rake 4 Indian function, trace function III) are the function control circuit group xaK.
Yo J! ll11-grei.

The control unit 2J, which controls the console interface, is the console side where the main function is realized.

The φ control unit LJ, which generates various rounding control signals and tie-in signals that connect each other to the system mode L, uses various status information (f signals) output from the processor unit 11 to control fW set points. 11, which determines the execution mode (system mode or console mode), is also O. The output control signal (1) is input to the driver/receiver (data bus driver ZS>K,
The data on the path 31 is controlled. In addition, the control signal is sent to the system side and is sent to the driver/receiver 27.
- Pass line JJ - Supplied to console innoturf ace circuit group 16 via driver/reggie/snack 1#.

The circuit 11J# that controls the console Inter 7 Ace is
By various control signals obtained from the console unit]
, performs mode designation and mode switching control for the processor unit 11.

As stated above, by having the console interface circuit group 16 on the system side, the console unit 16 can be easily connected.

In this case, the system is completely console-based.
) is placed under the control of J. All accesses to the various functions and systems are made via the keys from the console unit 1 or the display circuit 5. i9, Console 291111Cf Various functions can be added by implementing a programmable ROM. The functions possessed by the console unit and the console unit are the same as those described in the prior art section, and are redundant, so a description thereof will be omitted here.

FIG. 3 shows an embodiment of the internal circuit configuration of the console interface control section shown in FIG. 2. In FIG. 0, 31 is a command detector. Commands output from the processor unit 11 are supplied to the command detector 31 via path twin SOs (muscles 11.D and -D7), and the transition mode is analyzed here, the results of which will be described later. Set to 7 rigs and 70 dd groups. In addition, All~
mnti, an address line through which an address output from the processor unit 11 is propagated;

D. to D are bidirectional data lines, which are used in time division with the address lines of the lower eight pits.

The above transfer modes include RUN (continuous execution of the system program), 5TEP (single step execution of the system program), and 0FFT (R@ad/write to system memory/input/output map).
.

There are four types of ETCF (other search functions, etc.). These pieces of information are 70” and 7” respectively.
J J # J J # J 4 p J 5 is supplied as a single unit.

3# is the RUN control enclosure.

This circuit 3# includes pass cycle statuses 25* to 25* to J and cu status outputted from the processor unit y)zz. S...Qsl is input, and in the above transition mode, the pass cycle status 8 (1-g* is output from the processor unit, t II 8 shown in Table 1.
There are 11 types of d-sustatus. In addition, the keys Q8...Q81 are processor unit 1).
This status indicates the execution status of the processor unit 7J (D instruction), and there are four types of execution status shown in Table 2.

(Table 2) Details of the operation of the processor 11 can be found in the ``1PX'' published by Intelja Mother Corporation on August 20, 1981
Please refer to ``367 A49 Edesmani Al''.

On the other hand, Jl is r-), which means Hermitage! A command for generating an interrupt (a master interrupt with the highest priority) is detected.

This r-tzrK is executed in single-step execution by TIP, system! Program O Addition - 11TOP when stopped, BRKe and other 7b-0 stops when breakpoint function is specified @ITC
A code is supplied, and any one signal is detected to activate the nine and turtle,) ai [I generation @SZ. The NMI generator 38 outputs an NMI interrupt signal based on the r-to-sr output. This NMI interrupt signal! In addition to being supplied to the processor unit lllIC, 4 are supplied to the RU 111 set/reset and control path S-. 39 is NMI
This is a table detection circuit. This circuit 3g detects the Nil [1 interrupt key address and turns off the RUN signal (signal for rounding the execution selection of the system program or console! Roderam, RUN se,)/reset F
It has a function of instructing the control circuit 36.

In the present invention, the NM1 interrupt is used to return the execution mode of the processor 11 from system program execution to console program execution. In addition, each output of the Arizzoflo, De32 to j5 is supplied with r-toy 4mK, and the r-toy0 output is supplied as a 1x signal to the Zoro7, Sauni,
is supplied to port 11. The RUN signal specifies whether the grosser unit 11 is in console mode or system mode. In the embodiment of the present invention, "01 is console mode;
Indicates the "t'ti system mode." When set to '0', the program built in the console unit 1 is executed, and various data can be input or functions can be specified using keys &-14. On the other hand, when @1m, a system program is executed or an input/output device is accessed.

In addition, 41 to 41 indicate the amount of dry nozzle and the receiver (in the figure, Du
41 is f-), 41 is a path control unit.

The input/output signal groups of each driver and receiver 41 to 47 are interfaces connected to the system KII, and all of them except CL[ have been explained. CLK is a system clock output from system mode J, and various signals in the console 22 and controller are output from this CLK.
K) will be scanned and synchronized with the system.

Hereinafter, the operation of the ninth embodiment shown in FIG. 3 will be explained in detail with reference to the timing charts shown in FIGS. 4 to 7.

If, the transition operation from console mode to system mode will be explained. A system mode transition command is detected from the key 4, and the gross unit 11 outputs a command corresponding to the transition mode onto the path 30. The command detection circuit 31 analyzes the transition mode, and supplies the results to each of the remote controllers fsx to 3i.

Assume that the RUN or 5TEP signal is output as a result of the analysis. In this case, the timing charts in Figures 4 and 5)
As shown in (timing when RUN signal turns ON),
IRKT (l1fflCRRUPT)
If it is defined as either the RIc-URN) or JMP (JUMP) command, the RUN ON timing will be determined depending on the execution form of each command.

Note that which command is used depends on the state of the system at that time. The IRET instruction prefetches an effective address from the stack memory existing on the system side. In the case of a JMP command (specifying the start address on the system side using console commands), JMP command execution IL Q
The status of S・+QS1 becomes MTY, and if it is set to system mode at the time of running, the system program can be executed continuously (in the figure, the 8Y8T PROGRAM section). . If the transfer mode is 87EP, then Ki.

- Decoy when Status outputs the first byte! Generates an interrupt. As a result, the console mode is entered after executing one instruction. In addition, T in the figure! indicates the idle state of the path.

! 1lliIR1 which can be understood at this timing is the transition expansion to the system mode by the Rrr instruction as shown in Figure S.
:RU at the first operand fetch after T instruction 7 etching
Turn on N. When the IIET command enters the system mode, it will appear on the starboard @ll (@・d・8*gmn+at)
, IP (Imstrmctlsm P@imt@
r) Pop the contents of the t flag and start execution from the corresponding address. Single status! will be forced back to console mode after one command depth.

Figure 6 shows 0FFT, that is, system side memory and input/output pins! This shows the 1i tie at the time of R@a d /'Wr 1 t. This mode is on the system side! Enter system mode without running LogTsum at all. Execute the li@s/Writ command (memory, input/output device) on the console side, and
During etching, the WET signal is turned on to set the system mode. Therefore, there is no need to go into console mode! Do not use interrupts.

The controller that controls the above operation is the RUN shown in Figure 3.
This is a control circuit. ζO circuit 1# is supplied with pass cycle 7 status S・~8 禦 and cu status Q8・eQsl), and according to the transition mode,
Setting/resetting and opening the flip f70dde J2-15 is as described above).

Next, the operation of trapping from system mode to console mode will be described. This operation is performed by generating image side crowding as described above. NMI generator 3
The NMI signal issued by HUF 8 is supplied to the non-maskable interrupt line of the processor unit 1. As is well known, this interrupt is processed as an interrupt with the highest priority of up to 4. Detects a command to generate an interrupt. 5TEP is input in single step, f execution.

Further, to stop the continuous execution of the system log, a TOP signal is input to another circuit (not shown).

If the break lnd function is specified, a BRK signal is sent from a break lnd detection circuit (not shown). There is also some other function stop signal mtc.

Here, if any signal is detected, the NMI generator 3
From 8 to RUN set/reset, the front side rush is issued at an optimal timing while taking into consideration the timing of the control circuit 36.

FIG. 7 shows the mode switching skin iminda at the time of occurrence of go. Zorosessa Uni, 1-11 is between! When the signal is detected, after the execution of the instruction at that point is completed, the contents of the iIP and 7 ladders currently in use are saved onto the disk. After that, the interrupt processing subroutine address stored in the NMI interrupt table is set to 78. Chi. The NMI table detection circuit 39 shown in FIG. 3 detects the NMI interrupt table address. Then, the decoy signal is turned OFF and the subroutine address (e8 e
IF). After the 7-etch is completed, Ishi and Process, Sauni, and To11 execute the console program.

As a result, Oiley I can use the keypad 4 and display circuit 5 to search for various information or issue the next instruction.

〔Effect of the invention〕

As described in theory v4 above, the console unit can be configured with a simple bar and door by having a control program externally and controlling the front signal. t
In addition, by implementing a simple interface on the system, connection with the system console unit can be easily made. Other effects obtained by the present invention are listed below.

(1) Previously existing department stores and gools were expensive and had problems in appearance, but the console that implements the present invention is inexpensive and can be developed in a short period of time, which has a great positive impact on system development. give.

(2) Since it can be configured compactly, it can be used as a maintenance tool.

(3) Functional expansion of the console itself is also IIs.

In addition, in the embodiment of the present invention, 80
Although the 88 microgrocer has been described as an example, the console unit can be constructed in a similar manner for any other microgrocer. It is also possible to connect an inspection unit to a nine-system system equipped with a microprocessor using a console interface in which the present invention is implemented. This is also effective when performing system trouble analysis during inspection.

[Brief explanation of the drawing]

Figure 1 shows the information and abuse system in which the present invention is realized.
FIG. 2 is a block diagram showing an embodiment of an apparatus for implementing the present invention; FIG. 3 is a block diagram showing the internal circuitry of the nine console-in-skin-face control section shown in FIG. 2; For example, FIGS. 4 to 7 are tie charts showing the operation of the present invention.

Claims (3)

[Claims] (1) A system consisting of a first memory unit in which the system program is stored, and a single processor unit stored in this memory unit and connected to the system based on the nine-nogram, and controlling each unit? The above system is connected to the -do via a path, and the above system? - Circuit group 1 that performs interface control with the board, circuit group 2 that realizes the console's original functions based on the built-in console unit control program, and the address space of the above system program are allocated with an O/4 lag. For console control! A console unit consisting of a second memory unit in which the program code is stored, and a second memory unit in which the system is stored; Or fa that is characterized by console control
Durham execution control method. (2) The circuit group 1 transfers to the external program execution mode; receives the cloak, and receives the command detection circuit that performs this mode analysis; group, the pass status outputted by the processor unit and its own status information are input, and the transfer mode is applied to the above 7 lip flops! and a control circuit that performs group set control and selects execution of a system program or a =yy source program! program execution control method. (3) The circuit group 1 includes a y-t for detecting a non-maskable interrupt (NMI) instruction specified from the outside;
When this r-) output becomes significant, an NMI interrupt is notified to the fkyo processor. The processor unit is characterized in that the processor unit accepts the returned books and switches from the system program to the console program Oi line. control method.