JPS58137256A - Insulated gate semiconductor device - Google Patents
Insulated gate semiconductor deviceInfo
- Publication number
- JPS58137256A JPS58137256A JP57018751A JP1875182A JPS58137256A JP S58137256 A JPS58137256 A JP S58137256A JP 57018751 A JP57018751 A JP 57018751A JP 1875182 A JP1875182 A JP 1875182A JP S58137256 A JPS58137256 A JP S58137256A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- field plate
- conductor
- drain
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は絶縁ゲート牛導体装置、脣に高J11!rfL
為出力MO8F]IfT(金属識化膜牛魯体電昇効来ト
ランジスタ)q)相互変調歪改善技術[@する。[Detailed Description of the Invention] The present invention is an insulated gate conductor device, with high J11! rfL
Intermodulation distortion improvement technology [@.
&出力用のM ’08 F E Tとして萬1図に示す
ように、、ガえはPJl181基体10嵌面に互いに離
隔して形成したN型愼域2.3tンース、ドレインとし
、ソース・ドレイン間の基体表面の−すに薄い酸化膜(
810m膜)4に介してMO尋e)耐熱金lII&から
成るゲート電極5t−設はゲートとソース。& Output M'08 FET As shown in Figure 1, the gap is a 2.3t N-type region formed at a distance from each other on the fitting surface of the PJl181 substrate 10, and a source and a drain. A very thin oxide film (
810m film) 4 through MO layer) Gate electrode 5t made of refractory gold lII & source.
ドレイン間の81基体の表面に上記グー)t−マスクと
して自己壷金的に形成し7tMfJ層6,7を形成する
。このMg2層のうちソース−N鳩は冒−直のN+層6
とし、ドレイン1IllN層は光分に関°噛tとって低
−直の^耐圧化N一層7とする。上記ゲート5及びN′
+層b a M一層7の上を犀い絶縁捩8で覆い、ソー
ス2及びドレイン3にそれぞれオーミック・コンタクト
(抵抗接触)するム111極9.10t−設ける。ソー
ス陶のムl電極9IIiゲートを越えて高耐圧化に一層
7の一部上に延在させてフィールドプレート11とする
。On the surface of the substrate 81 between the drains, the 7tMfJ layers 6 and 7 are formed by forming the above-mentioned t-mask in a self-containing manner. Of this Mg2 layer, the source-N layer is the exposed N+ layer 6.
The drain 1IllN layer is made of a low-voltage breakdown layer 7 with respect to the light component. Gate 5 and N'
+ layer b a M layer 7 is covered with a thin insulating screw 8, and a layer 111 and a pole 9.10t are provided to make ohmic contact (resistance contact) with the source 2 and drain 3, respectively. The field plate 11 is formed by extending beyond the source ceramic electrode 9IIi gate and over a part of the layer 7 to increase the withstand voltage.
このようなフィールドプレート11會有する高出力MO
8FITにおいては、フィールドプレートは双極形MO
87ITの第2ゲートとして動作することか考えられ、
その出力特性はIIz図に夷−で示すごとく2段折れ曲
りのめ力波形も双極形MO8FICTのそれと全く同じ
形態であられれる。High power MO with 11 such field plates
In 8FIT, the field plate is a bipolar MO
It is thought that it may operate as the second gate of 87IT,
As for its output characteristics, the two-stage bending force waveform is exactly the same as that of the bipolar type MO8FICT, as shown by the symbol "-" in Figure IIz.
すなわち、−図において、■は非飽和領域でこれはチャ
ネル部(纂1図の12)の特性と高耐圧化層(オフセッ
トN一層))の抵抗によって支配される。ソースドレイ
ン電圧vD8か同図の点?/l11v、&tで示す界域
でチャネルはピンチオフし電流か飽和し絶1飽和II場
■に入る。第1飽和領域まではチャネル部の特性か王と
して働き本来MCIIFITのもつドレイン電流工。0
2乗特性に近いもの會示す。しかしドレイン電圧vD1
r上昇さゼるとフィールドプレートと基板によって高耐
圧化層はピンチオフし点fllvDPt境に第2飽和領
域■に入る。That is, in the - figure, (2) is a non-saturation region, which is dominated by the characteristics of the channel portion (12 in Figure 1) and the resistance of the high breakdown voltage layer (offset N layer). Source drain voltage vD8 or the point in the same figure? /l11v, &t, the channel pinches off, the current saturates, and enters the absolutely saturated field II. Up to the first saturation region, the characteristics of the channel part function as the main drain current, which is originally part of MCIIFIT. 0
It shows something close to a square-law characteristic. However, the drain voltage vD1
When r increases, the high breakdown voltage layer is pinched off by the field plate and the substrate and enters the second saturation region (2) at the boundary of point fllvDPt.
このIi2飽和領域ではチャネル部の特性に高耐圧化層
の特性か加わるため2乗特性からずれると考えられる。In this Ii2 saturation region, the characteristics of the high breakdown voltage layer are added to the characteristics of the channel portion, so it is thought that the characteristics deviate from the square-law characteristics.
この徒、ブレークダ9.ン電圧VBri1してブレ領域
ズ9ン餉域■となる。This fellow, Breakda 9. When the voltage VBri1 is increased, the blur region becomes a blur region (9).
このようにフィールドプレートの影響で疑似の飽和特性
領域(B) tもつことによシよりa−工G5%性か2
乗特性から外れるi!来、MO8FK12)工MD(相
互変幽歪)か大きくな9%性上好ましくない。In this way, due to the influence of the field plate, it is possible to have a pseudo saturation characteristic region (B) t.
i deviates from the power characteristic! Since MO8FK12) engineering MD (mutual metamorphosis distortion) is large 9%, it is unfavorable.
本発明は上記した点にかんがみて疑似飽和特性領域tな
くし、工MD%性を同上し几i16胸波簡出力MoaP
ITの提供を目的とする。In view of the above-mentioned points, the present invention eliminates the pseudo-saturation characteristic region t, improves the mechanical MD% property as above, and achieves a simple chest wave output MoaP
The purpose is to provide IT.
以下果m−にそって本発明を詳述する。The present invention will be described in detail below along with the advantages.
前述した如くにフィールドプレー14するMO8FET
におけるIMDI改善する几めKは菖2飽和餉域の出力
抵抗【大きくして(脣性a−t#!2図の破−で示すよ
うに飽和領域部分t+坦して)纂1飽和愼域の2乗特性
か第2飽和餉域lでm待できるように丁ねばよいと考え
られる。出力抵抗を大きくする几めには、(1)基板不
純物−ft−大きくする。(2)高耐圧化N一層へのイ
オン打込量を少なくする、(3)フィールドプレート直
下の歎化躾厚會小さくする、(4)フィールドプレート
長を大きくする等の諸手段か考えられる。しかし、上記
(1)はドレイン耐圧の低下tまねき、(2)はソース
ドレイン飽和電圧の増加f破壊に弱くなり、(3)は谷
11i01.I8の増加を招き、又(4)は破壊強mo
m下會米た丁等それぞれ間mがある。し大かつて高耐圧
でttm特件の低下させないで工MDt改豐する新しい
構造か求められる。MO8FET with field play 14 as mentioned above
The method to improve IMDI in K is to increase the output resistance of the 2nd saturation region (by increasing the saturated region t + flattening the saturated region part t + as shown by the broken part in Figure 2). It is considered that the square characteristic of , or the second saturation region l, should be set so that m can be waited. To increase the output resistance, (1) increase the substrate impurity -ft-. Possible measures include (2) reducing the amount of ion implantation into the high-voltage N layer, (3) reducing the amount of ion implantation directly below the field plate, and (4) increasing the field plate length. However, (1) causes a decrease in the drain breakdown voltage, (2) increases the source-drain saturation voltage and makes it vulnerable to breakdown, and (3) causes the valley 11i01. It causes an increase in I8, and (4) increases the destructive strength mo
There is a time interval between each meeting. However, there has been a need for a new structure that can improve the MDt without reducing the TTM characteristics due to the high withstand voltage.
113図は本発明による高周波高出力MOIiiFIT
q1UA場的構造を示すものである。Figure 113 shows the high frequency high output MOIiiFIT according to the present invention.
This shows the q1UA field structure.
本発v4によればフィールドプレートに起因する纂2胞
和餉域O出力抵抗を大きくする手段として谷ji ’
i a 11 t−増加することなくフィー、ルドプレ
ート下g)w&犀T。x1ft小嘔〈するために、同図
のようにフィールドプレート直下の戚化換離のみt博く
する。すなわち纂5図−)〜←)の一部プロセスに示す
ように、(a)ゲート酸化膜4の上KMoケート5ai
形成し、このゲート5atマスクとして自己整合的にド
レイン1iIilK高耐圧N一層7.ソース冑にN+層
6t−形成する。(b)気相よpH化#M8at形成し
、基板表面よりの膜厚T。xlが4000ム稲度となる
ようにし、その上に第2 e)M oゲート5bt−形
成する、(0)新たに厚く酸化flL8bt形属し、基
41表面よりの膜厚T0工、調9000ム棚友となるよ
うKする、(d)ソース・ドレイン@2,3にコンタク
トホトエッチを行なうとともに第2のMQゲー)51)
の上の酸化膜8bにスルーホールtiけ、ムt11−蒸
着してソース電極9.ドレイン電極1(l設ける。とと
4にソース電極9に延設するフィー・ルドプレー)11
’i形成する。According to the present invention v4, as a means to increase the output resistance caused by the field plate, the valley ji '
i a 11 t-field without increase, under the plate g) w & rhino T. In order to reduce the height by 1 ft, widen only the relative displacement directly below the field plate as shown in the same figure. That is, as shown in part of the process in Figs.
The drain 1iIilK high breakdown voltage N single layer 7. is formed in a self-aligned manner using this gate 5at mask. An N+ layer 6t- is formed on the source layer. (b) pH-adjusted #M8at is formed in the gas phase, and the film thickness T from the substrate surface. xl is 4000 μm, on which a second e) Mo gate 5bt is formed, (0) a new thick oxidized flL8bt type, film thickness T0 from the surface of the base 41, thickness 9000 μm. (d) Perform contact photoetch on the source and drain @2 and 3 and create a second MQ gate) 51)
A through hole is made in the oxide film 8b on top of the oxide film 8b, and a source electrode 9. is formed by vapor deposition. Drain electrode 1 (provided with a field electrode extending to the source electrode 9 at and 4) 11
'i form.
このようなMO81FITの構Iitによれば、フィー
ルドプレート直下の酸化alJIT0工、のみt博くす
ることができ、その部分でe)シきい亀電圧V t h
t低くすることになる。前記した疑似飽和111iI域
に緻化躾厚T0工、に大きく依存する。この場合に欧化
−厚を薄くシフを部分はフィールドプレート直下部に限
られ、他の部分全厚く形成しである几め容量0166k
”大きく増加することかない。According to the structure of MO81FIT, only the oxidized aluminum JIT0 section directly under the field plate can be increased, and in that part e) the threshold voltage V t h
It will be lowered by t. It is largely dependent on the densification thickness T0 in the pseudo-saturated 111iI region described above. In this case, the European version is thinner and the part that is shifted is limited to the area directly below the field plate, and the other parts are all thicker.The reduced capacity is 0166k.
``It's not going to increase significantly.
第2飽和慎域の出力抵抗を大きくする他の手段として、
1M3図に示すように、チャネル部及びフィールドプレ
ート直下部を含みP−基板の一部にP19+7zル12
i形成する。この場合のPウエル不純物a度は5xlO
”/cd穆度としP−基板のそれよりも高いtaX<低
抵抗)となる。これにょ9第23@和電圧vPはウェル
一基板一度N1と高耐圧N一層(Pウェル1it)のd
lllfN、□で決まり、−万態和電圧vDBはウェル
の形成された基板一度’4mとウェルIll!度で決ま
り、耐圧と出力抵抗會別々にW&訂することかできる。As another means of increasing the output resistance of the second saturation limit,
As shown in Figure 1M3, P19+7z12 is attached to a part of the P-board including the channel part and directly below the field plate.
i form. In this case, the P-well impurity a degree is 5xlO
``/cd degree of purity and taX<low resistance) which is higher than that of the P-substrate.In this case, the 9th 23rd @sum voltage vP is equal to the d of the well one substrate once N1 and the high breakdown voltage N one layer (P well 1it).
It is determined by lllfN, □, and the -all-conditions voltage vDB is once '4m on the substrate where the well is formed and the well Ill! It is determined by the degree of resistance, and the withstand voltage and output resistance can be adjusted separately.
上配実施向で述べ九本発明によれは疑似飽和籍性領域か
ない几め入出力骨性か2乗特性になり。According to the present invention described in the above-mentioned implementation direction, there is no pseudo-saturation region, and the input/output becomes a square-law characteristic.
2乗特性になることにより工MD%性が向上する。By becoming a square-law characteristic, the engineering MD% property is improved.
纂4図は幻数曲−による入出力骨性を示し、曲自ムに2
乗になる状廊、曲縁Bは2乗より大きい状、at示す。Figure 4 shows the input/output characteristics according to the phantom number song, and the song itself has 2
The shape of the curved edge B is larger than the square, and the curved edge B is larger than the square.
このような工MD特性C)同上により本発明にょhば良
好なIJ ニア増幅器の製造か可能となった。Due to such engineering and MD characteristics (C) as above, it is possible to manufacture a better IJ near amplifier according to the present invention.
本発明は高周波高出力用MO1i1F]CTの全てに適
用でき、そ(D @ K I M K 55以下の低周
波用を含むリニア増幅器用MO日FICTK応用できる
ものである。The present invention can be applied to all MO1i1F]CTs for high frequency and high output, and can be applied to MOFICTKs for linear amplifiers, including those for low frequencies of 55 or less.
菖1図はこtNまでの高出力m08F1丁を硬式化した
断面図、第2図は高出力MO8F]CTにおける電流−
亀圧籍性【示す曲線図、$IE3図は本発明によるMO
87I?(り原珊的栴造を示す断面図、514図は対数
化した入出力特性曲鎌図、第5図+a+〜ldlは本発
明によるMO8F]Il’!’の一部製造プロセスを示
すニー#面図である。
l・・・P−製基板、2・・・ソース、3・・・ドレイ
ン、番・・・ゲート絶嶽皺、5・・・MOケート、6・
・・N 層、7・・・高耐圧化N一層、8・・・絶縁膜
、9・・・ソース電極、10・・・ドレインll極、1
1・・・フィールドプレート、12・・・Pウェル。
代壇人 1士 薄 1)利 窄″
第 1 図
第 2 図
第 3 図
第 4 図
1、、 ve、。
入寓力才斗十主Figure 1 is a cross-sectional view of one hardened high-output m08F up to tN, and Figure 2 is the current in the high-output MO8F CT.
Tortoise pressure property [Curve diagram shown, $IE3 diagram is MO according to the present invention]
87I? (Cross-sectional view showing Rihara Sanku's Seizo, Figure 514 is a logarithmized input/output characteristic curve diagram, Figure 5 +a+~ldl is MO8F according to the present invention) Knee# showing a part of the manufacturing process of Il'!' FIG.
...N layer, 7...N single layer with high withstand voltage, 8...Insulating film, 9...Source electrode, 10...Drain II pole, 1
1...Field plate, 12...P well. Figure 1, Figure 2, Figure 3, Figure 4, Figure 1,, ve,.
Claims (1)
体と導電型の異なる2つの牛導体領域ソース・ドレイン
の間の牛昏体基体表面上の一部に薄い絶縁girt介し
てゲート電極を設け、ゲートと上記ソース・ドレインと
の間の牛導体基体表面に基体と導1Effilの異なる
牛導体層を形成してその一部1#lt−高耐圧化層とし
、ソース・ドレインにそわぞれ抵抗接触する電極層全形
成するとともに、一方の電極層をゲート電極の上を越え
て高耐圧化層の絶縁換上に5イールドプレートとして延
在させた絶縁ケート牛都体11fllにおいて、上記フ
ィールドプレート直下の絶縁−の展厚會フィールドプレ
ート下でない高耐圧化層上の絶縁編のそれよaS<する
ρ・、フィールドプレート下の高耐圧化層の不H智*1
IEkフィールドプレート下でない高耐圧化層のそれよ
りも小さくかつフィールドプレート下の基板不純W嫌戚
tフィールドプレート下でない基板のそれよりも大きく
することで、フィールドプレートにより飽和する領域ま
で出力の二乗特性を保持できるよう圧したことを特徴と
する絶縁ゲート午昏体装置。1. A gate electrode is formed through a thin insulating girth on a part of the surface of the cow conductor substrate between the substrate and two conductor regions of different conductivity types, source and drain, which are formed on the surface of the cow conductor substrate at a distance from each other. A conductor layer with a different conductor from the base is formed on the surface of the conductor base between the gate and the source/drain, and a part of it is made into a 1#lt-high breakdown voltage layer, which is applied to the source/drain. In 11 fl.s. The thickness of the insulation directly under the field plate is that of the insulation layer on the high voltage withstand layer that is not under the field plate.
By making the IEk smaller than that of the high breakdown voltage layer that is not under the field plate and larger than that of the substrate that is not under the field plate, the square characteristic of the output is reduced to the region where it is saturated by the field plate. An insulated gate body device characterized by being pressurized to hold.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57018751A JPS58137256A (en) | 1982-02-10 | 1982-02-10 | Insulated gate semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57018751A JPS58137256A (en) | 1982-02-10 | 1982-02-10 | Insulated gate semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58137256A true JPS58137256A (en) | 1983-08-15 |
Family
ID=11980346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57018751A Pending JPS58137256A (en) | 1982-02-10 | 1982-02-10 | Insulated gate semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58137256A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6046658U (en) * | 1983-09-06 | 1985-04-02 | 富士電気化学株式会社 | Cylindrical battery metal container |
US5198964A (en) * | 1990-09-27 | 1993-03-30 | Hitachi, Ltd. | Packaged semiconductor device and electronic device module including same |
JPH09219512A (en) * | 1995-12-02 | 1997-08-19 | Lg Semicon Co Ltd | MOS field effect transistor and manufacturing method thereof |
WO2004012270A3 (en) * | 2002-07-31 | 2004-04-15 | Motorola Inc | Field effect transistor and method of manufacturing same |
EP1336989A3 (en) * | 2002-02-18 | 2004-06-02 | Infineon Technologies AG | Transistor device |
JP2014523649A (en) * | 2011-07-05 | 2014-09-11 | 日本テキサス・インスツルメンツ株式会社 | Monolithically integrated active snubber |
US20190148231A1 (en) * | 2016-04-12 | 2019-05-16 | Sun Yat-Sen University | Mos transistor for suppressing generation of photo-induced leakage current in active channel region and application thereof |
-
1982
- 1982-02-10 JP JP57018751A patent/JPS58137256A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6046658U (en) * | 1983-09-06 | 1985-04-02 | 富士電気化学株式会社 | Cylindrical battery metal container |
US5198964A (en) * | 1990-09-27 | 1993-03-30 | Hitachi, Ltd. | Packaged semiconductor device and electronic device module including same |
JPH09219512A (en) * | 1995-12-02 | 1997-08-19 | Lg Semicon Co Ltd | MOS field effect transistor and manufacturing method thereof |
EP1336989A3 (en) * | 2002-02-18 | 2004-06-02 | Infineon Technologies AG | Transistor device |
WO2004012270A3 (en) * | 2002-07-31 | 2004-04-15 | Motorola Inc | Field effect transistor and method of manufacturing same |
US6870219B2 (en) | 2002-07-31 | 2005-03-22 | Motorola, Inc. | Field effect transistor and method of manufacturing same |
JP2014523649A (en) * | 2011-07-05 | 2014-09-11 | 日本テキサス・インスツルメンツ株式会社 | Monolithically integrated active snubber |
US20190148231A1 (en) * | 2016-04-12 | 2019-05-16 | Sun Yat-Sen University | Mos transistor for suppressing generation of photo-induced leakage current in active channel region and application thereof |
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