JPS58124834U - Intermittent pseudo failure generating device - Google Patents
Intermittent pseudo failure generating deviceInfo
- Publication number
- JPS58124834U JPS58124834U JP2157382U JP2157382U JPS58124834U JP S58124834 U JPS58124834 U JP S58124834U JP 2157382 U JP2157382 U JP 2157382U JP 2157382 U JP2157382 U JP 2157382U JP S58124834 U JPS58124834 U JP S58124834U
- Authority
- JP
- Japan
- Prior art keywords
- generating device
- pseudo
- intermittent
- failure generating
- pseudo failure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は、この考案の一実施例を示すブロック図である。
１・・・スキャン回路、２・・・命令解読回路、３・・
・反送データ作成回路、４・・・命令トレース回路、５
・・・擬似障害発生判断回路、６・・・パラメータ読込
みメモリおよびレジスタ、７・・・パラメータ解読回路
、−−８・・・パラメータ編集回路、９・・・パラメー
タ蓄積メモリおよびレジスタ、１０・・・擬似障害発生
位置確認回路、１１・・・擬似障害発生回数カウンタ、
１２・・・擬似障害データ作成回路、１３・・・返送デ
ータ送出回路。The figure is a block diagram showing an embodiment of this invention. 1...Scan circuit, 2...Instruction decoding circuit, 3...
・Reverse transmission data creation circuit, 4...Instruction trace circuit, 5
. . . Pseudo-failure occurrence determination circuit, 6 . . . Parameter reading memory and register, 7 . . . Parameter decoding circuit, -- 8 .・Pseudo-fault occurrence position confirmation circuit, 11... pseudo-fault occurrence counter,
12...Pseudo failure data creation circuit, 13...Return data sending circuit.
Claims (1)
置の間にわける制御信号、データ信号を、あらかじめ前
記擬似障害発生装置内に入力されたパラメータにより、
固定的または間欠的に、１回またはランダムに、または
時間をおいてくり返し擬似障害を設定および制御、ある
いは擬似障害発生の間欠的故障位置を設定することを可
能としたことを特徴とする間欠的擬似障害発生装置。The control signals and data signals that are divided between the control device connected to the central processing unit and the pseudo fault generating device are controlled by parameters input in advance into the pseudo fault generating device.
An intermittent system characterized by making it possible to set and control pseudo-failures fixedly or intermittently, once or randomly, or repeatedly over time, or to set the intermittent fault location where pseudo-faults occur. Simulated failure generating device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2157382U JPS58124834U (en) | 1982-02-19 | 1982-02-19 | Intermittent pseudo failure generating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2157382U JPS58124834U (en) | 1982-02-19 | 1982-02-19 | Intermittent pseudo failure generating device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58124834U true JPS58124834U (en) | 1983-08-25 |
Family
ID=30033690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2157382U Pending JPS58124834U (en) | 1982-02-19 | 1982-02-19 | Intermittent pseudo failure generating device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58124834U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0253143A (en) * | 1988-08-17 | 1990-02-22 | Nec Corp | Pseudo fault generating system |
-
1982
- 1982-02-19 JP JP2157382U patent/JPS58124834U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0253143A (en) * | 1988-08-17 | 1990-02-22 | Nec Corp | Pseudo fault generating system |
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