JPS58123747A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58123747A JPS58123747A JP592282A JP592282A JPS58123747A JP S58123747 A JPS58123747 A JP S58123747A JP 592282 A JP592282 A JP 592282A JP 592282 A JP592282 A JP 592282A JP S58123747 A JPS58123747 A JP S58123747A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- leads
- inner lead
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000008188 pellet Substances 0.000 claims description 9
- 229910010293 ceramic material Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 1
- 239000011521 glass Substances 0.000 abstract description 10
- 230000008018 melting Effects 0.000 abstract description 10
- 238000002844 melting Methods 0.000 abstract description 10
- 239000000919 ceramic Substances 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
- H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法ｋＩＩし、４１＃ＩＣセ
ラミツクパツケージ瀧の半導体装置に好適な製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device manufacturing method kII, which is suitable for manufacturing a semiconductor device in a 41# IC ceramic package.
半導体装置、中でもサーディツプと称するセラミックパ
ッケージ瀝の半導体装置は、第１図にその構造を示すよ
うに、セラζツク材からなるペース１にリードフレーム
２および半導体素子ベレット３を固着し、かつリードフ
レーム２のインナーリード（ポスト１ｍ）２ｍとベレッ
ト３の電極パッドとをワイヤ４にて接続した上でセフイ
ックキャップ５を装着して内部を封止するよう和した構
成である。この場合、リードフレーム２はコパールヤ４
２アａイ等の金属板材を打抜あるいはエツチングにて成
形ないし折重加工し、低融点ガラスを利用して前記ベー
スＩＩＣ溶着している。また、ベレット３とリードフレ
ーム雪とのワイヤ４１１１！ＩＣ際しては、リードフレ
ーム若しくはベースの全体的な位置、更に必要とあれば
ベレットの位置を認識した上でワイヤボンダにより殆ん
ど自動的に行なうよ５にしているのである。As shown in FIG. 1, a semiconductor device, especially a ceramic packaged semiconductor device called a cerdip, has a lead frame 2 and a semiconductor element pellet 3 fixed to a paste 1 made of ceramic material, and a lead frame In this configuration, the inner lead (post 1 m) of 2 m and the electrode pad of the pellet 3 are connected with a wire 4, and then a safety cap 5 is attached to seal the inside. In this case, lead frame 2 is copper layer 4
A metal plate material such as 2A is formed or folded by punching or etching, and is welded to the base IIC using low melting point glass. Also, the wire 4111 between the bellet 3 and the lead frame snow! When forming an IC, the overall position of the lead frame or base and, if necessary, the position of the pellet are recognized, and the process is almost automatically carried out using a wire bonder.
ところで、近年の半導体装置では、ベレットに形成した
集積回路の高集積化に伴なってリード数（ビン数）が増
大し、１００ビン、２００ビン級のものが提供されてき
ている。このため、同一寸法のパッケージを前提とすれ
ば、リード数の増大に伴なりてリード幅寸法を小さくす
る必要があり、アウタリードおよびインナーリードか細
−化される。このように、リードが細幅化されると、リ
ードフレームはその機械的な強度が低下して僅かな外力
によっても変形され易くなり、第１図からも判るようＫ
ｌｆ＃にインナーリード２ａ＠にはアウタリード２ｂ側
のような連絡片（フレーム）６が形成されていないこと
からその変形は着しい。したがって、このような状態で
リードフレーム２をペースＩＫ取着すれば、堆層時の条
件の相違によって各ベース毎にインナーリード位置にば
らつきが生じ、ベースやリードフレームの全体的な位置
に対する各インナーリード位置を一定に保持することが
できなくなる。この結果、ベース中り−ドフレー五の全
体的な位置の認識のみで各インナーリード位置を認識す
ることはできなくなり、ワイヤボンディング時には各イ
ンナーリード位置を１個づつ測定する必要が生じてワイ
ヤボンダに構成の複雑なものが要求されると共一作業効
率が低下し、さらにインナーリード同士がシ謬−トした
りしてワイヤボンデインダの信頼性が低下するという問
題がある。また、リードフレームが変形された状して残
存し、低融点ガラスに作用して疲労破壊の原因となるお
それもある。Incidentally, in recent semiconductor devices, the number of leads (number of bins) has increased as the integrated circuits formed on pellets have become more highly integrated, and devices with 100 bins and 200 bins have been provided. Therefore, assuming that the package has the same size, as the number of leads increases, the lead width must be reduced, and the outer leads and inner leads are made thinner. As the lead width becomes narrower, the mechanical strength of the lead frame decreases and becomes easily deformed by even the slightest external force.
Since the connecting piece (frame) 6 unlike the outer lead 2b side is not formed on the inner lead 2a@ in lf#, the deformation is severe. Therefore, if the lead frame 2 is mounted by pace IK in such a state, the inner lead position will vary from base to base due to differences in the conditions during deposition, and the position of each inner lead will vary with respect to the overall position of the base and lead frame. It becomes impossible to hold the lead position constant. As a result, it is no longer possible to recognize the position of each inner lead just by recognizing the overall position of the base hole and the frame, and it becomes necessary to measure each inner lead position one by one during wire bonding, which makes it difficult to configure the wire bonder. If a complicated wire bonder is required, there is a problem that the efficiency of the wire bonder decreases, and the reliability of the wire bonder decreases because the inner leads may become loose. Further, there is a risk that the lead frame remains in a deformed state and acts on the low melting point glass, causing fatigue failure.
したがクズ本発明の膳的は、複数個のインナー□ リー
ドな連結片を介して一体く連結した状態にリードフレー
ムを形成しておき、このリードフレームをベースに取着
した後に前記連結片を切除し℃各インナーリードな切離
することｋより、リードのＩｓ＠化に伴なり℃生ずるり
−ド７レー五の変形およびインナーリード位置のばらつ
きを防止し、これｋより各インナーリード位置を一定に
保持して多リード半導体のワイヤがンディングを従来と
同等のワイヤボンダにて行なうことを可１１ｉ！にし、
作業効率中信頼性の低下を防止することができる半導体
装置の製造方法を提供することにある。However, the object of the present invention is to form a lead frame integrally connected via a plurality of inner □ lead connecting pieces, and after attaching this lead frame to a base, the connecting pieces are attached. By cutting each inner lead, it is possible to prevent the deformation of the lead and the variation in the position of the inner lead, which occurs when the lead becomes Is@, and to prevent the position of each inner lead from being It is possible to hold the wires of multi-lead semiconductors constant and bond them with a wire bonder equivalent to the conventional wire bonder! west,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent a decrease in reliability during work efficiency.
以下、本実−を図示の実施例により説明する。The present invention will be explained below with reference to illustrated embodiments.
第２図四〜（至）は本−―方法なデ島アルインライン朧
のセラ建ツクパッケージの半導体装置に適用した実施例
の工場図を示している。同Ｅ＾において、１Ｇはセラ電
ツク材からなるベースで、全体を長方形の板状に形成し
、その中央にはキャビティ１１を凹設し工底面に金めり
きを施している。Figures 2 to 4 show a factory diagram of an embodiment in which this method is applied to a semiconductor device in a ceramic construction package. In the same E^, 1G is a base made of ceramic electric material, and the whole is formed into a rectangular plate shape, and a cavity 11 is recessed in the center, and the bottom surface is plated with gold.
會た、１２はリードフレームであり、コバールや４２７
０イ等の薄金属板を打抜きあるいはエツチング等により
複数本のリードを形成し、かつこれを断面コ字状に折−
形成している。これらのり−ド１３は夫々インナーリー
ド１４とアウタリード１５とからなり、インナーリード
１４の先端をリードフレーム１２の中心位置近傍に配置
する一方、アクタリードの先端をリードフレーム１２０
両側辺に並設記章し工いる。そして、前記インナーリー
ド１４の各先端は略方形の連結片１６の四周囲に一体に
連結し、各先端がこの連結片１・を介して連結している
。また、前記アウタリード１ｓの先端は直線状の連結枠
１７に夫々一体に連結した構成としている。換言すれば
前記リード１３の成形時にこれら連結片１６と連結枠１
フをリード１３と共に一体に成形するのであり、これに
よりリードフレーム１２は多少の外力が加えられても容
易に変形することはない。12 is a lead frame, Kovar and 427
A plurality of leads are formed by punching or etching a thin metal plate such as 0I, and then folded into a U-shaped cross section.
is forming. Each of these leads 13 consists of an inner lead 14 and an outer lead 15. The tip of the inner lead 14 is placed near the center of the lead frame 12, while the tip of the actuator lead is placed near the center of the lead frame 120.
There are parallel insignias on both sides. Each tip of the inner lead 14 is integrally connected to the four peripheries of a substantially rectangular connecting piece 16, and each tip is connected via this connecting piece 1. Further, the tips of the outer leads 1s are each integrally connected to a linear connecting frame 17. In other words, when molding the lead 13, these connecting pieces 16 and the connecting frame 1
The lead frame 12 is not easily deformed even if some external force is applied thereto.
このように形成したリードフレーム１２は、次に同図（
至）のように、ベー°ス１０の周辺に配設した低融点ガ
ラス１８にてベースｉｏ、ｋＫ固着する。The lead frame 12 formed in this way is then shown in the same figure (
As shown in (to), the bases io and kk are fixed with a low melting point glass 18 disposed around the base 10.
この場合、ペース１０全体を図外のヒータを用いて加熱
して低融点ガラス１８を軟化させた状態でリードフレー
ム１２をベース上に抑圧して固着することは言う壇でも
ない。と九により、リードフレーム１２はベースｌ０ｖ
ｃ固定され、リード１２．４１にインナーリード１４は
ベースに対し１不動の状態とされ、連結片１６Ｋｍ［絖
されていることのために、インナーリード同士の位置関
係は変化されることはない。In this case, it is unnecessary to heat the entire paste 10 using a heater (not shown) to soften the low melting point glass 18, and then suppress and fix the lead frame 12 on the base. and 9, the lead frame 12 has a base l0v
c is fixed to the lead 12.41, and the inner lead 14 remains immovable with respect to the base, and the connecting piece 16 km [is wired, so the positional relationship between the inner leads does not change.
しかる後ｋ、第３図の平面図の破線のよ５ｋ、各インナ
ーリードの先端位置にある連結片１６を例えばレーず光
を用いて咎先端を結ぶ―＃ＩＣＧって切断し、第２図０
のようにリードフレーム１２から連結片１６を切除する
。連結片１６を切除するととｋより、各インナーリード
１４は夫々切離されて独立状態とされる。しかしながら
、このように切離され℃も各インナーリード１４は既に
低融点ガラス１８にてベース１０＃ｃ固着されているの
で特にその先端位置が変化されることはない。Thereafter, as shown by the broken line in the plan view of FIG. 3, the connecting piece 16 at the tip of each inner lead is cut using, for example, a laser beam to connect the tip of the inner lead. 0
Cut the connecting piece 16 from the lead frame 12 as shown in FIG. When the connecting piece 16 is removed, each inner lead 14 is separated from each other and becomes independent. However, since each inner lead 14 is already fixed to the base 10#c with the low melting point glass 18 even after being separated in this way, the position of its tip is not particularly changed.
以上のよ５ｋｃしてリードフレーム１２を固着した後、
同図００よ５ｖｃ、前記キャビティ１１内に半導体素子
ベレッ）１９ｖ通常の方法により固着し、次いでこのペ
レット１９の電極パッド２０とインナーリード１４の先
端とをワイヤ２１にて接続する。この際、ワイヤボンダ
はベース１０中リードフレーム１２の全体的な位ｔを認
識し、この位置認識と予め与えられたリードフレーム形
状等の情報とで各インナーリードの先端位置を認識する
ことができ、ペンツ１１９０位置認鐵とｋよって従来と
同様の自動ワイヤポジディングを行なうことができる。After fixing the lead frame 12 by 5kc as above,
00, the semiconductor element pellet 19v is fixed in the cavity 11 by a conventional method, and then the electrode pad 20 of this pellet 19 and the tip of the inner lead 14 are connected with a wire 21. At this time, the wire bonder recognizes the overall position t of the lead frame 12 in the base 10, and can recognize the tip position of each inner lead based on this position recognition and information such as the lead frame shape given in advance. Automatic wire positing similar to the conventional method can be performed using the Pentz 1190 positioning iron.
その後、同図備のようにセラミックキャップ２２をペー
ス１０上に槓せてこれを低融点ガラス２３にて固着して
内部な封止ｆ、６一方、アク−リード１５先端の連結幹
１７を切除すれば半導体装置が完成されるのである。Thereafter, as shown in the figure, a ceramic cap 22 is placed on the pace 10, and this is fixed with a low melting point glass 23 to seal the interior f, 6.Meanwhile, the connecting stem 17 at the tip of the Acrylic lead 15 is cut out. Then, the semiconductor device is completed.
したがって、以上の一連の製造方法によれば。Therefore, according to the above series of manufacturing methods.
つてインナーリード１４、％にその先端の変形が防止さ
れるので、リード数が増大してリードが細幅化された場
合でもインナーリード先端位置が変化されることはなく
、ペース１０に固着したときｋも先端位置にばらつ會が
生ずることはない、このため、各インナーリード先端位
置、つまりワイヤ２１を接続するポスト舊を認識する場
合にも各先端位置な個々に測定する必要はなく、リード
フレーム１２の全体位置若しくはリードフレーム１２と
ペース１Ｇの位置関係が既知の場合はペースｌＯの位置
を認識すれば予め与えられたリードフレーム形状（リー
ドフレーム全体に対する各インナーリード先端の相対位
置）と相俟って各先端位置の認識を行なうことができる
。これにより、ワイヤボンダはリードの細幅化ｋかかわ
らず従来と同様のものを使用することかで１、ワイヤボ
ンダの構造の複雑化を防止すると共ｋ、各インナーリー
ド先端位置を夫々測定する必要がないのでワイヤボンデ
ィングＩＩｃ％する作業工数の増大を防止して作業効率
を向上しかつ一層では棗好なワイヤボンディングを行な
って製品の信頼性を向上することができるのである。This prevents the tip of the inner lead from deforming to 14%, so even if the number of leads increases and the lead width becomes narrower, the position of the tip of the inner lead will not change, and when it is fixed at pace 10. Therefore, when recognizing the tip position of each inner lead, that is, the post end to which the wire 21 is connected, there is no need to measure each tip position individually. If the overall position of the frame 12 or the positional relationship between the lead frame 12 and the pace 1G is known, by recognizing the position of the pace 1O, it can be matched with the pre-given lead frame shape (relative position of each inner lead tip with respect to the entire lead frame). The position of each tip can be recognized by looking down. As a result, the same wire bonder as the conventional wire bonder can be used despite the narrowing of the lead width, which prevents the structure of the wire bonder from becoming complicated and eliminates the need to measure the tip position of each inner lead. Therefore, it is possible to prevent an increase in the number of man-hours required for wire bonding, thereby improving work efficiency, and furthermore, by performing efficient wire bonding, it is possible to improve the reliability of the product.
ｌＩＫ、Ｉ）−ドフレームの変形を防止するので。lIK, I) - to prevent deformation of the frame.
低融点ガラス１８によるペースｌＯへの固着状態で変形
に伴なう内部応力がリードに生ずることもなく、低融点
ガラスやその鵠の部位Ｋ＞ける疲労破壊を防止すること
もできる。When the low melting point glass 18 is fixed to the paste 10, no internal stress is generated in the lead due to deformation, and it is also possible to prevent fatigue failure of the low melting point glass or its part K.
ここで、各インナーリードの先端を一体状態に連結して
お（連結片は、第４図に示すような環状の連結片１６Ａ
とし工もよく、この場合には同図の破纏で示す部分を切
断するととｋなる。また、連結片の切除に際しては、前
述したレーず光を利用するのが最も有効であるが、マイ
クロカッタを利用した機械的な切断方法中エツチング等
の化学的な方法を利用することもできる。Here, the tips of each inner lead are integrally connected (the connecting piece is an annular connecting piece 16A as shown in Fig. 4).
It is also good to cut the part, and in this case, the part shown in the same figure as the broken part will be cut out. Further, when cutting the connecting pieces, it is most effective to use the laser beam described above, but it is also possible to use a mechanical cutting method using a micro cutter or a chemical method such as etching.
更に１本例ではデ凰アルインライ／ｆｆｌのパッケージ
を示したが、リードフレームをペースｋｌ１着した後ベ
レットとリードとの関にワイヤボンディングを行な５方
法を採用する半導体装置であれは、フラット層のパッケ
ージの様なものであっても本実−を適用することがで館
る。Furthermore, although this example shows a flat-layer in-lie/ffl package, if the semiconductor device adopts the method 5 in which wire bonding is performed between the bullet and the lead after the lead frame is attached to the lead frame, a flat layer Even if it is something like a package, you can apply the real truth.
以上のよう＃ＩＣ本発明の製造方法によれば、複数個の
インナーリードな連結片を介して一体に連結した状態に
リードフレームを形成しておき、このリードフレームを
ペースに取着した後ＷＣ＠Ｚ連結片を切除して各インナ
ーリードを切離しているので、リードの細幅化によりて
もリードフレームの変形およびペース固着状態でのリー
ド位置のばらつきが−することはなく、これによりペー
スに対する各リードの固着位置精度を向上し、ワイヤボ
ンディング作業を害鳥ｋかつ良好な効率で行なうと共に
製品の信頼性を高めることができるという効果を奏する
。As described above, according to the #IC manufacturing method of the present invention, a lead frame is formed in a state of being integrally connected via a plurality of inner lead connecting pieces, and after this lead frame is attached to a pace, the WC @Since each inner lead is separated by cutting off the Z connection piece, even if the lead width is made narrower, there will be no deformation of the lead frame or variation in lead position when the pace is fixed, and this will prevent the lead from changing the pace. This has the effect of improving the fixing position accuracy of each lead, making wire bonding work less harmful and more efficient, and improving the reliability of the product.
第１図は従来方法を示す斜視図、第２図四〜（ト）は本
発明のニーを示す斜視図、第３図は連結片近傍の拡大平
面図、第４図は連結片の異なる形状の平面図である。
ｌＯ・・・ペース、１１・・・キャビティ、１２・・・
リ−−ドフレーム、１３・・・リード、１４・・・イン
ナーリード、１５・・・アウタリード、ＩＬ１６Ａ・・
・連結片、１７・・・連結枠、１８・・・低融点ガラス
、１９・・・ペレット、２１・・・ワイヤ、２２・・・
キャップ・第 １ 図
第 ２ 図（Ｂ）
第 ２ 図（Ｄ）
第 ２ 図（Ｅ）
第 ３ 図
／、／
／４
第 ４ 図
／ｌFIG. 1 is a perspective view showing the conventional method, FIG. FIG. lO...pace, 11...cavity, 12...
Lead frame, 13...Lead, 14...Inner lead, 15...Outer lead, IL16A...
- Connection piece, 17... Connection frame, 18... Low melting point glass, 19... Pellet, 21... Wire, 22...
Cap/Figure 1 Figure 2 (B) Figure 2 (D) Figure 2 (E) Figure 3/, / /4 Figure 4/l
Claims (1)
ムと半導体素子ベレットを固着しかつり−ドフレー五の
インナーリードとベレットとをワイヤ接続する半導体装
置の製造方法ｋ＞いて、前記リードフレームは複数本の
インナーリードな連結片を介して一体に連結形成した状
態で前記ベース上に固着し、固着完了後に前記連結片を
切除して各インナーリードな切離影威したことを特徴と
する半導体装置の製造方法。1. A method for manufacturing a semiconductor device in which a lead frame and a semiconductor element pellet are fixed on a paste made of ceramic material or the like, and the inner lead of a defrayer and the pellet are connected by wire. A semiconductor device, characterized in that the semiconductor device is fixed on the base in a state of being integrally connected via inner lead connecting pieces, and after the fixing is completed, the connecting pieces are cut off to effect separation of each inner lead. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP592282A JPS58123747A (en) | 1982-01-20 | 1982-01-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP592282A JPS58123747A (en) | 1982-01-20 | 1982-01-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58123747A true JPS58123747A (en) | 1983-07-23 |
Family
ID=11624381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP592282A Pending JPS58123747A (en) | 1982-01-20 | 1982-01-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123747A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115853A (en) * | 1985-11-15 | 1987-05-27 | Mitsui Haitetsuku:Kk | Manufacture of lead frame |
| EP0623957A4 (en) * | 1992-11-24 | 1995-04-19 | Hitachi Construction Machinery | PROCESS FOR PRODUCING A MOUNTING FRAME. |
-
1982
- 1982-01-20 JP JP592282A patent/JPS58123747A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115853A (en) * | 1985-11-15 | 1987-05-27 | Mitsui Haitetsuku:Kk | Manufacture of lead frame |
| EP0623957A4 (en) * | 1992-11-24 | 1995-04-19 | Hitachi Construction Machinery | PROCESS FOR PRODUCING A MOUNTING FRAME. |
| US5548890A (en) * | 1992-11-24 | 1996-08-27 | Hitachi Construction Machinery Co., Ltd. | Lead frame processing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3902148A (en) | Semiconductor lead structure and assembly and method for fabricating same | |
| US4994411A (en) | Process of producing semiconductor device | |
| US4026008A (en) | Semiconductor lead structure and assembly and method for fabricating same | |
| EP0247644A1 (en) | Integrated circuit die-to-lead frame connection using an intermediate bridging member | |
| US4987473A (en) | Leadframe system with multi-tier leads | |
| US3893158A (en) | Lead frame for the manufacture of electric devices having semiconductor chips placed in a face to face relation | |
| EP0497744B1 (en) | Metal heat sink baseplate for a resin-encapsulated semiconductor device, having raised portions for welding ground connection wires thereon | |
| US5309018A (en) | Lead frame having deformable supports | |
| US4743956A (en) | Offset bending of curvaceously planar radiating leadframe leads in semiconductor chip packaging | |
| US4415917A (en) | Lead frame for integrated circuit devices | |
| US5408127A (en) | Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components | |
| JPH09129808A (en) | Plastic molded semiconductor device and its manufacture | |
| JPS58123747A (en) | Manufacture of semiconductor device | |
| US3395447A (en) | Method for mass producing semiconductor devices | |
| JP2528192B2 (en) | Semiconductor device | |
| JP2564596B2 (en) | Method for manufacturing semiconductor device | |
| JP2504187B2 (en) | Lead frame | |
| EP0077276A2 (en) | Method for fabricating a hybrid circuit module | |
| JPH1140728A (en) | Lead frame and electronic component using the same, and manufacture thereof | |
| JPS6388833A (en) | Tape-carrier mounting tape | |
| JPH06350013A (en) | Lead frame, semiconductor device and manufacture of semiconductor device | |
| JPH0821650B2 (en) | Method for manufacturing semiconductor device | |
| JP2564595B2 (en) | Method for manufacturing semiconductor device | |
| EP0644585A2 (en) | Lead frame and method of manufacturing the same | |
| JPS621239A (en) | Semiconductor device |