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JPS58123131A - Input device - Google Patents

Input device

Info

Publication number
JPS58123131A
JPS58123131A JP57006310A JP631082A JPS58123131A JP S58123131 A JPS58123131 A JP S58123131A JP 57006310 A JP57006310 A JP 57006310A JP 631082 A JP631082 A JP 631082A JP S58123131 A JPS58123131 A JP S58123131A
Authority
JP
Japan
Prior art keywords
resistor
terminal
group
power supply
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57006310A
Other languages
Japanese (ja)
Other versions
JPS628808B2 (en
Inventor
Hideo Saito
秀雄 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57006310A priority Critical patent/JPS58123131A/en
Publication of JPS58123131A publication Critical patent/JPS58123131A/en
Publication of JPS628808B2 publication Critical patent/JPS628808B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/22Static coding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE:To reduce noise and unnecessary radiation and to decrease the number of wirings between a switch group and a digital circuit 4, by constituting such a matrix that DC voltages are applied to key contacts. CONSTITUTION:Row lines 2a, 2b, 2c, and 2d of the key switch group 1 are connected to one terminal +V of a power source through resistances 5a, 5b, 5c, and 5d respectively. Further, the row lines 2a-2d are connected to input terminals of voltage comparators 6a-6d having a threshold voltage V1 and their outputs are connected to the input terminal part 4c of the digital circuit 4. Column lines 3a-3d, on the other hand, are connected to the other terminal G of the power source through resistance groups 7a, 7b, 7c, and 7d as well as the row lines 2 and further connected to the input terminal part 4D of the digital circuit 4 through voltage comparators 8a-8d.

Description

【発明の詳細な説明】 本発明は、複数の列線と行線の交点に接点をもつ、いわ
ゆるマトリックス11の入力装置に関し、雑音を発生し
にくい、筺た、不要輻射の少ない入力装置を提供するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called matrix 11 input device that has contact points at the intersections of a plurality of column lines and row lines, and provides an input device that is less likely to generate noise, has less noise, and has less unnecessary radiation. It is something to do.

従来、複数の列線と行線の交点に接点(キー)を■する
キー入力装置には、スタティク型と、ダイナミック型が
あり、スタティク型は、接点に直流′屯田が印加される
為、雑音の発生や不要輻射は少ないが、接点を開閉する
だめのスイッチとそれを入力するディジタル回路間の配
線本数が多くなるという欠点を持っている。
Conventionally, there are static and dynamic types of key input devices that make contacts (keys) at the intersections of multiple column lines and row lines.The static type has no noise because a direct current is applied to the contacts. However, it has the disadvantage that it requires a large number of wires between the switch that opens and closes the contact and the digital circuit that inputs it.

第1図にダイナミック型入力装置の従来例を示す。1は
、マトリックス状に接点を配したキースイッチ群であり
、その行線群2はディジタル回路4の出力端子部4Aに
接続されている。ここでディジタル回路4は、例えばマ
イクロコンピュータである。
FIG. 1 shows a conventional example of a dynamic input device. Reference numeral 1 denotes a key switch group having contacts arranged in a matrix, and its row line group 2 is connected to an output terminal section 4A of a digital circuit 4. Here, the digital circuit 4 is, for example, a microcomputer.

一万列(13はディジタル回路4の入力端子部4Bに接
続されている。ディジタル回路の出力端子部4Aには第
2図に示すようなパルス状の電圧が印加される。しかし
ながら上記ダイナミック型は、マトリックス状に接点を
設けるので、接点を開閉するスイッチとディジタル回路
間の配線本数は少ないが、接点にパルス状の交流′電圧
が印加される為、ittを発生しやすく、又不要輻射の
発生の原因ともなるという欠点を持っている。
The 10,000 column (13 is connected to the input terminal section 4B of the digital circuit 4. A pulse voltage as shown in FIG. 2 is applied to the output terminal section 4A of the digital circuit. However, the above dynamic type Since the contacts are arranged in a matrix, the number of wires between the switch that opens and closes the contacts and the digital circuit is small, but since a pulsed AC voltage is applied to the contacts, it is easy to generate itt and unnecessary radiation. It has the disadvantage that it can also cause

本発明は、上記従来の欠点を解消し、接点に直流電圧を
印加する方式で雑音や不要輻射の発生の原因をなくすと
ともに、接点をマトリックスに組んだ新規な入力装置を
提供するものである。以下本発明の一実施例を図面にも
とづいて説明する。
The present invention solves the above-mentioned conventional drawbacks, eliminates the cause of noise and unnecessary radiation by applying a DC voltage to the contacts, and provides a novel input device in which the contacts are arranged in a matrix. An embodiment of the present invention will be described below based on the drawings.

第3図は第1の実施?11を示す回路図であり、1のキ
ースイッチ群の行線2a、2b、2c、2dは、それぞ
れ抵抗5a、6b、5c、5dを介して′電源の一端+
■に接続されている。また行線2a。
Is Figure 3 the first implementation? 11, the row lines 2a, 2b, 2c, 2d of the key switch group 1 are connected to one end of the power supply + via resistors 5a, 6b, 5c, 5d, respectively.
■Connected to. Also, row line 2a.

2b、2c、2dはvlの閾値電圧をもつ電圧比較器6
a、6b、6c、6dのそれぞれの入力端子に接続され
ており、電圧比較器6a、6b、6c。
2b, 2c, 2d are voltage comparators 6 with a threshold voltage of vl.
The voltage comparators 6a, 6b, 6c are connected to the respective input terminals of the voltage comparators 6a, 6b, 6c, and 6d.

6dの出力はディジタル回路4の入力端子部4Cに接続
されている。一方列線3a、3b、3c。
The output of 6d is connected to the input terminal section 4C of the digital circuit 4. On the other hand, column lines 3a, 3b, 3c.

3dも行線群2と同iに、それぞれ抵抗群7a。Similarly to row line group 2 and i, 3d is a resistance group 7a.

7b、7G、7dを介して電源の他端Gに接続されてお
り、また、■2の閾値電圧をもつ′電圧比較器それぞれ
aa、ab、be、sciを通して、芳ジタル回路4の
入力端子部4Dに接続されている。
It is connected to the other end G of the power supply via 7b, 7G, and 7d, and is also connected to the input terminal section of the aromatic circuit 4 through the voltage comparators aa, ab, be, and sci, respectively, which have a threshold voltage of 2. Connected to 4D.

ここで電圧比較器6a、6b・・・ハ、コンハレータI
C,演算増幅器等を用いて容易に構成することも可能で
あるが、本実施例では、CMOSインバータを用いてい
る。この場合、閾値電圧v1゜v2は、CMOSインバ
ータに加える電源電圧を変えることにより容易に設定可
能である。
Here, voltage comparators 6a, 6b...C, conhalator I
Although it is possible to easily configure the inverter by using a CMOS inverter, an operational amplifier, etc., in this embodiment, a CMOS inverter is used. In this case, the threshold voltage v1°v2 can be easily set by changing the power supply voltage applied to the CMOS inverter.

一つもキーが押されていない場合は、行線2a。If no key is pressed, line 2a.

・・・の電圧はキースイッチ部の電源′電圧Vとなる。... becomes the power supply voltage V of the key switch section.

ここで電圧比較器6a・・・6dの閾値電圧V、をvl
〈Vに設定すると、行線2a・・・2dは全てH“ルベ
ルとなる。また列線群3の電圧はOvとなり、電圧比較
器8a・・−a dの閾値電圧v2を■2〉oに設定す
ると、列線群3は”L”レベルとなる。
Here, the threshold voltage V of the voltage comparators 6a...6d is vl
<When set to V, the row lines 2a...2d all become H" level. Also, the voltage of the column line group 3 becomes Ov, and the threshold voltage v2 of the voltage comparators 8a...-a d is set to ■2>o When set to , the column line group 3 becomes "L" level.

次に、キースイッチが押された場合を考える。Next, consider the case where a key switch is pressed.

例えば、キースイッチ1bCが押された場合を考える。For example, consider a case where key switch 1bC is pressed.

電源+Vより抵抗6bを通し、行線2b。Pass the resistor 6b from the power supply +V to the row line 2b.

スイッチIbc列線3Cを経て、抵抗7Cを通して電流
が流れる。従って、抵抗6bの抵抗値をR1゜vl・v
2を に設定すると、行線2bは“L″レベル列線(支)は″
Hルベルとなり、キースイッチ1 haが押されたこと
を検出できる。
Current flows through switch Ibc column line 3C and through resistor 7C. Therefore, the resistance value of the resistor 6b is set to R1゜vl・v
2 is set to , the row line 2b is "L" level and the column line (support) is "
H level, and it is possible to detect that the key switch 1 ha has been pressed.

即ち、前述の1IA1111¥1.電圧の榮件と組み合
わせ、vl・v2を に設定することにより、スイッチが押されたか否かの検
出ができる。
That is, the above-mentioned 1IA1111¥1. By combining with the voltage condition and setting vl and v2, it is possible to detect whether the switch has been pressed.

上記の構成によれば、キースイッチ1aa〜1ddには
直流電圧が印JJnされる為、従来のような雑音の発生
、或いは不要輻射の発生のない入力装置が実現できる。
According to the above configuration, since a DC voltage is applied to the key switches 1aa to 1dd, it is possible to realize an input device that does not generate noise or unnecessary radiation unlike the conventional input device.

さらに従来のスタティック型とは異なりキースイッチが
マトリックスに配置されているため、ディジタル回路4
への配−数が少ないという大きな利点がある。
Furthermore, unlike the conventional static type, the key switches are arranged in a matrix, so the digital circuit 4
It has the great advantage of requiring less number of devices.

第4図は、本発明のg2の実施例であり、第1の実施例
をさらに改良し、閾値電圧の異なる電圧比較器を用いな
い画素な構成を特徴とするものである。
FIG. 4 shows a g2 embodiment of the present invention, which is a further improvement of the first embodiment and is characterized by a pixel configuration that does not use voltage comparators with different threshold voltages.

キースイッチ群1の列d3a 、3b 、3a 、sd
は抵抗7を通して電源Gに接続されると共に直接ディジ
タル1o回路4の入力端子に接続されている。
Rows d3a, 3b, 3a, sd of key switch group 1
is connected to the power supply G through a resistor 7 and directly to the input terminal of the digital 1o circuit 4.

一方行線2a〜2dは、抵抗6a〜6d全通して電源+
Vに接続されると共に、それぞれダイオード61a、抵
抗62a(その他61b、62b等)の直列回路を通し
て電源Gに接続され、ダイオード61aと抵抗62aの
接続点からディジタル回路4(本実施例ではマイクロコ
ンピュータ)の入力端子部4C・に入力されている。
One row of lines 2a to 2d connects the resistors 6a to 6d with the power supply +
V, and is also connected to the power supply G through a series circuit of a diode 61a and a resistor 62a (others 61b, 62b, etc.), and connects the digital circuit 4 (microcomputer in this embodiment) from the connection point of the diode 61a and resistor 62a. is input to the input terminal section 4C.

ここで、ディジタル回路4の入力端子部4Cの閾値電圧
をV、r、ダイオード61a〜61dの順方向′電圧を
vL)とする。また抵抗62a〜62dの抵抗値R3を
抵抗6a〜6dの抵抗値H1に比較して十分大きくする
と、キーが押されていないときのディジタル回路4に入
力される行d2a〜2dの電圧は、V−V、となり、引
線の′電圧は0となる。
Here, it is assumed that the threshold voltage of the input terminal portion 4C of the digital circuit 4 is V, r, and the forward direction' voltage of the diodes 61a to 61d is vL). Furthermore, if the resistance value R3 of the resistors 62a to 62d is made sufficiently larger than the resistance value H1 of the resistors 6a to 6d, the voltage of the rows d2a to 2d input to the digital circuit 4 when no key is pressed is V -V, and the voltage of the lead wire becomes 0.

これより閾値電圧vTの条件として、 0 (VT(: V−VL) となる。From this, as a condition for the threshold voltage vT, 0 (VT(:V-VL) becomes.

となる。becomes.

従って、閾値電圧vTがト記2つの榮往を満足するよう
にR1,R2を選定すれば、キースイソナが押されたこ
とを検出できる。またダイオード61a〜61dは、閾
値電圧v、rの範囲に余裕があれば抵抗におきかえるこ
とも可能となる。
Therefore, if R1 and R2 are selected so that the threshold voltage vT satisfies the above two conditions, it is possible to detect that the key isona is pressed. Further, the diodes 61a to 61d can be replaced with resistors if there is margin in the range of the threshold voltages v and r.

1 第6図は、本発明の第3の実施例でめり、第2の実施例
に比較して、dl、R2の選定に余裕を持たせたもので
ある。本実施例では行線群については第2の実施例と同
一に構成されている。また引線群についても、行線群と
全く同じ構成である。すなわち、列線3aは抵抗7&を
介して′41.源の一端Gに接続され、かつ逆方向ダイ
オード81aと抵抗82aの直列回路を通してこの電源
Gに接続され、さらに前記ダイオード81aと抵抗82
aの接続点からディジタル回路4の入力端子部4Dに入
力されている。他の列線3b〜3dについても同様であ
る。
1. FIG. 6 shows a third embodiment of the present invention in which dl and R2 are selected with more leeway than in the second embodiment. In this embodiment, the row line group has the same structure as in the second embodiment. Furthermore, the drawing line group has exactly the same structure as the row line group. That is, the column line 3a is connected to '41.' through the resistor 7&. It is connected to one end G of the power supply, and is connected to this power supply G through a series circuit of a reverse diode 81a and a resistor 82a, and further connected to the power supply G through a series circuit of a reverse diode 81a and a resistor 82a.
The signal is input to the input terminal section 4D of the digital circuit 4 from the connection point a. The same applies to the other column lines 3b to 3d.

ここで閾+1[i’に圧の条件として、キーが押されて
いない場合は、抵抗82a〜82dの抵抗l1fR4を
抵抗値H2に比較して十分大きくすると、vD<v、、
(v−vD キーが押された場合は となる。従って、閾値電圧vTは、第2の実施例に比較
して、条汀がゆるくなり、1(1,1(2の選定に余裕
がでてくる。またダイオード81a〜g1dは、第2の
実施例の場合と同様に抵抗におきかえることも可能であ
る。
Here, as a pressure condition for the threshold +1[i', when the key is not pressed, if the resistance l1fR4 of the resistors 82a to 82d is made sufficiently large compared to the resistance value H2, vD<v,
(If the v-vD key is pressed, then Furthermore, the diodes 81a to g1d can be replaced with resistors as in the second embodiment.

L記の実施例からも明らかなように本発明は、キー接点
に直流゛電圧を印加した方式で、マトリックスを組むも
のであるから、雑音や不要輻射が非常に少なく、さらに
スイッチ肝とディジタル回路間の配線本数も少ないキー
人力装置が実現できる。
As is clear from the embodiment described in L, the present invention uses a method in which a direct current voltage is applied to the key contacts and forms a matrix, so noise and unnecessary radiation are extremely low. A key human-powered device with fewer wires can be realized.

また本発明は特にディジタル回路がマイクロコンピュー
タなどの場合にも有用である。1チツプマイクロコンビ
ーータでは入力端子数出力端子数があらかじめ設定され
ているため、応用例によっては、出力端子が不足し、入
力端子に余裕がある場合がある。従来のマトリックス方
式の人力装置では、出力端子と入力端子の両方を便用す
るのに対し、本発明によノ1ば入力端トのみに接続口■
詣で複雑な回路を必四とせずに人力装置f1:構成でき
るものである。
The present invention is also particularly useful when the digital circuit is a microcomputer or the like. Since the number of input terminals and the number of output terminals are set in advance in a one-chip microcombinator, depending on the application, there may be a shortage of output terminals and a surplus of input terminals. In conventional matrix-type manual devices, both output terminals and input terminals are conveniently used, but the present invention has a connection port only at the input terminal.
It is possible to construct the human-powered device f1 without necessarily requiring complicated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の人力装置の回路図、第2図はその要部波
形図、dXa図は本発明の一実施例の回路図、第4図、
第5図はそれぞれ他の実施例の回路図である。 1・・・・・・キースイッチ群、2−・・・・・行線柱
、2 a 、 2 b 、 2 c 、 2 d 60
600m行線、3−−−−−−列線群、3a 、 3b
 、 3c 、 ad *、、、、、列線、4C14D
 、−−−−−入力端子部、5a、5b、6c、5d・
・・・・・抵抗、6a、8b、6c、6d・・・・・・
電圧比較器、7a、了す、7c、7d・・・・・・抵抗
、8 a 、 8 b 、 8 c 、 8 d −−
−−−−電圧比較器、61a。 61 b 、 61 C、61d−−−−−−ダイオー
ド、62a。 62b 、62C,62d 、−、、、、抵抗、81 
a、81 b。 81 c  81 d =ダイオード、82a+、82
b。 82c  82d・・・・・・抵抗。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名Wk
 1 図 第2図
Fig. 1 is a circuit diagram of a conventional human-powered device, Fig. 2 is a waveform diagram of its main parts, dXa diagram is a circuit diagram of an embodiment of the present invention, Fig. 4,
FIG. 5 is a circuit diagram of each other embodiment. 1...Key switch group, 2-...Row line column, 2a, 2b, 2c, 2d 60
600m row line, 3-------column line group, 3a, 3b
, 3c , ad *, , , , column line, 4C14D
, ---- Input terminal section, 5a, 5b, 6c, 5d・
...Resistance, 6a, 8b, 6c, 6d...
Voltage comparator, 7a, end, 7c, 7d... Resistor, 8 a, 8 b, 8 c, 8 d --
----Voltage comparator, 61a. 61b, 61C, 61d---diode, 62a. 62b, 62C, 62d, -,,, resistance, 81
a, 81 b. 81 c 81 d = diode, 82a+, 82
b. 82c 82d...Resistance. Name of agent: Patent attorney Toshio Nakao and one other person Wk
1 Figure 2

Claims (3)

【特許請求の範囲】[Claims] (1)複数の列線と、複数の行線とを有し、前記列線と
前記行線との交点にそれぞれ開閉可能な接点を設け、前
記列線をそれぞれ第1の抵抗群を通して、電源の第1の
端子に接続すると共に、第1の閾値電圧を有する第1の
電圧比較器群の入力端子に接続し、前記行線を、それぞ
れ第2の抵抗群を通して、前記電源の第2の端子に接続
すると共に、第2の閾値電圧を有する第2の電圧比較器
群の入力端子に接続し、前記第1.第2の電圧比較器群
の出力端子に前記接点の開閉状態を出力することを特徴
とする入力装置。
(1) It has a plurality of column lines and a plurality of row lines, and a contact point that can be opened and closed is provided at each intersection of the column line and the row line, and the column line is connected through a first resistor group, and a power supply is provided. and to the input terminal of a first group of voltage comparators having a first threshold voltage, the row lines being respectively connected to a second terminal of the power supply through a second group of resistors. terminal and to an input terminal of a second voltage comparator group having a second threshold voltage; An input device characterized in that the open/close state of the contact is output to the output terminal of the second voltage comparator group.
(2)複数の列線と、複数の行線とをゼし、前記列線と
前記性−との交点にそれぞれ開閉可能な接点を設け、前
8己列巌を、それぞれ第1の抵抗群を通して、電源の第
1の端子に接続すると共に、第2の抵抗或いは第1のダ
イオードと第3の抵抗を通して、前記′電源の第2の端
子に接続し、前記第2の抵抗或いは第1のダイオードと
IIII mL第3の抵抗との接続点を、ディジタルl
!:!回路の第1の入力端子部に接続し、前記行線を、
それぞれ第4の抵抗群を通して前記電源の第2の端子に
接続すると共に、前記ディジタル回路の第2の入力端子
部に接続したことを特徴とする入力装置。
(2) A plurality of column lines and a plurality of row lines are provided, contacts that can be opened and closed are provided at the intersections of the column lines and the lines, respectively, and the front 8 row lines are connected to the first resistance group. is connected to the first terminal of the power supply through a second resistor or a first diode and a third resistor, and is connected to the second terminal of the power supply through a second resistor or a first diode and a third resistor; Connect the connection point between the diode and the third resistor with a digital
! :! connected to the first input terminal portion of the circuit, and the row line is connected to the first input terminal portion of the circuit;
An input device characterized in that the input device is connected to a second terminal of the power source through a fourth group of resistors, and is also connected to a second input terminal section of the digital circuit.
(3)行線を、それぞれ第4の抵抗群を通して、電源の
第2の端子に接続すると共に、第5の抵抗或いは第2の
ダイオードと第6の抵抗を通して、前記′電源の第1の
端子に接続し、MiJ記第6の抵抗或いは第2のダイオ
ードと前記第6の抵抗との接続点をディジタル回路の第
2の入力端子部に接続してなることを特徴とする特許請
求の範囲第2項記載の入力装置。
(3) Connect the row lines to the second terminal of the power supply through the fourth resistor group, and connect them to the first terminal of the power supply through the fifth resistor or the second diode and the sixth resistor. and the connection point between the sixth resistor or the second diode of MiJ and the sixth resistor is connected to the second input terminal of the digital circuit. The input device according to item 2.
JP57006310A 1982-01-18 1982-01-18 Input device Granted JPS58123131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57006310A JPS58123131A (en) 1982-01-18 1982-01-18 Input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57006310A JPS58123131A (en) 1982-01-18 1982-01-18 Input device

Publications (2)

Publication Number Publication Date
JPS58123131A true JPS58123131A (en) 1983-07-22
JPS628808B2 JPS628808B2 (en) 1987-02-25

Family

ID=11634794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57006310A Granted JPS58123131A (en) 1982-01-18 1982-01-18 Input device

Country Status (1)

Country Link
JP (1) JPS58123131A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4843221A (en) * 1971-09-30 1973-06-22
JPS5431233A (en) * 1977-08-15 1979-03-08 Hitachi Ltd Switch information read-in circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4843221A (en) * 1971-09-30 1973-06-22
JPS5431233A (en) * 1977-08-15 1979-03-08 Hitachi Ltd Switch information read-in circuit

Also Published As

Publication number Publication date
JPS628808B2 (en) 1987-02-25

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