JPS58119669A - Method for manufacturing thin film semiconductor devices - Google Patents

Abstract

PURPOSE:To improve the characteristics of the thin film semiconductor device, by self-aligning source and drain regions with a gate wiring, thereby reducing gate drain capacity. CONSTITUTION:Positive type photoresist 12 is applied before the formation of amorphous silicon including N type impurities. Said resist is exposed by light transmitted from the back surface of an insulated substrate, with the gate wiring 10 as a mask, and a resist pattern 13, which is self-aligned with the gate wiring, is formed. Thereafter, an amorphous silicon film 18 including N type impurities is formed, and an amorphous silicon film 19 including unnecessary impurities in a channel region is lifted off by a resist pattern 17. Since the overlap of the gate wiring 21 and the drain region 24 is eliminated and the gate drain capacity is decreased, the response speed of the semiconductor is largely improved.

Description

[Detailed description of the invention] This f! J4C manufacturing method for manufacturing silicon *Related to a method for manufacturing thin film semiconductor devices.

For the purpose of the present invention, it is preferable to self-align the source and drain layers to the gate wiring. Gate. The purpose is to reduce the capacitance between the drains and improve the characteristics of the lock.

The details will be explained below with reference to the figures.

Figure 1 is a cross-sectional view of an amorphous silicon thin film semiconductor device fabricated using a conventional manufacturing method. In order to release the source 4 and drain 5, an amorphous silicon film containing N-type impurities was formed and then photo-etched, making it difficult to self-align with the gate wiring 2. can be. The excessive capacitance created in the overlapping area of gate wiring 2 and drain III region 50, which was created due to the photo-etching allowance, made the patent for the semiconductor device bad. In the figure, 1 indicates the insulation base. Y by sH vapor phase growth method
! / Made Kate acid? Experiment. Channel @ area consisting of 6ifJ completed morph silicon, 7,71j completed Lumi distribution is shown.

The thin film semiconductor of the present invention f: # by self-aligning the source and drain gA regions with the gate wiring %! , one thing is that it eliminates the drawbacks of the above i1r'.

Figure 2 and Figure 5 show the source and drain 1 in the starch syrup thin film semiconductor device! The formative force method of the l field is shown.

In the method of manufacturing a thin film semiconductor device of the present invention, as shown in FIG. As a mask, the resist pattern 15 self-aligned with the gate wiring is yV15! do. 11 shows the gate oxide film formed by vapor phase epitaxy. Then, as shown in FIG.
1 in Figure 1 for lifting off the amorphous silicon film 19 containing Ill impurities in the channel region, which is difficult to achieve by 1 in 7.
4ij shows the insulation base, 15 shows the gate wiring, and 16 shows the gate oxide film.

lI# manufactured by the manufacturing method of the present invention shown in upper P in Figure wI4
FIG. 3 is a cross-sectional view of the semiconductor neck. Kate 1st Experience 21 and Drain Territory #240 no longer overlap, gate.

Since the capacitance between the drains is reduced, the response delay 1 of the semiconductor device is greatly improved.

Gate oxide film formed by 22ij vapor phase growth method.

Amorphous silicon film 26.27ff'J aluminum arrangement 1 with source region 25 and channel region 25 The thin film semiconductor device manufactured by the manufacturing method of the present invention has a response compared to conventional thin film semiconductor devices. Since the slowness has been greatly improved, a thin film semiconductor device manufactured by the manufacturing method of the present invention can be incorporated into a clear crystal display panel, and it can be used not only for pixel switching transistors but also for peripheral circuits such as shift resists. It becomes possible to form it on the Ha calculation at once.

[Brief explanation of drawings]

Figure 1 shows a cross section of a thin film semiconductor device manufactured by a conventional manufacturing method.
It is Yl. v12 1. FIG. 5 is a diagram illustrating a method for changing the shape of the source and drain *m in the manufacturing method V of the thin film semiconductor device of the present invention. FIG. 4 is a cross-sectional view of the thin film semiconductor device according to the manufacturing method of the present invention. 1.9, 14.20... Insulation base 2.10, 15.21... Gate wiring 5.11, 16
．． 22...Gate oxide film 4.26...Source@Castle 5.24...Drain IJI# 6.25...Channel m list 7.8, 26.27...Aluminum wiring 12... Photoresist 15.17...Resist 18.19...More than M9 Morphous silicon Applicant Stock company 11D Seikokai agent Patent attorney Tsutomu Mogami Figure 1

Claims (1)

[Claims] There is absolutely no gate line formed on the substrate. #Gatel! !
I1, a gate acid filler formed by vapor phase growth on the line and . The gate acid f? An amorphous silicon 1I conductor with 9N crystalline conductors formed after #ν deposition and a lateral source and drain region. In a method for manufacturing a thin film array conductor device having a channel mound consisting of 11 AMOKONFURYOSUSHI. P
Gate acid film type 5! After O, the first wiring is positively glued as a jl+ff screen, and the dinut is passed through the insulating substrate to form a pattern. After that, a phosphorus silicon film containing N@ impurities was formed. 4. The resist pattern fE1j has a step of 11 steps off.
111. A method for manufacturing a thin film semiconductor device.