JPS58119228A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To adjust the time until a prescribed circuit operation of a semiconductor integrated circuit is completed after starting, by changing the gain constant and threshold voltage of an MOS transistor (TR) in the seiconductor integrated circuit even after manufacture. CONSTITUTION:In case of the adjusting mode, a drain of the MOS(TR)Q2 is connected to a node NH1, the source to a node NH2 and the gate to the node NH1 with a switch circuit 1, respectively. Further, a voltage difference VH larger than a power supply voltage VDD subtracted from a threshold value of the TRQ2 is applied between the drain and the source of the TRQ2, and the TRQ2 is conductive. In this case, the implantation of hot carrier to the gate oxide is caused in the TRQ2 and the characteristics of the TRQ2 is changed. The change is directed toward the reduced gain constant and the increased threshold voltage. Through this change, the discharge time constant of a capacitor C1 at the normal mode is increased and the input and output delay time is adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an MO
S) In a semiconductor integrated circuit equipped with a plurality of transistors, applying a voltage higher than normal to a specific transistor during an arbitrary period in which a predetermined circuit operation is not performed,
The present invention relates to a semiconductor integrated circuit in which the time from the start to the completion of a predetermined circuit operation can be adjusted by changing the gain i constant and threshold voltage of the transistor.

An example of a conventional semiconductor integrated circuit is shown in FIG.

This conventional semiconductor integrated circuit outputs the input signals φ and n when a certain time τ has elapsed since the input signals φ and n are input manually. In order to perform a predetermined circuit operation of generating , , four MOS transistors Q1 to Q4 and a capacitor C0 are mounted. P, , P2 are terminals 1 to which the power supply of voltage VDD is connected φ, are MOS) transistors Q1 to Q
The precharge signal, NL, NL2, which prepares the circuit formed by C4 and capacitor C7, is a node. As for the operation of the semiconductor integrated circuit shown in FIG.
1 to charge the capacitor c1. Next, when the human power signal φ1n becomes a high potential (vDD), the MOS transistor Q2 becomes conductive, and the capacitor C□ is discharged to the node N.
When the potential of L1 decreases and the potential of node NL becomes equal to or less than the threshold voltage (hereinafter expressed as v, h (C4)) of transistor Q4 (MOS transistor), output signal φ is generated. ut is at high potential (vD
D-vth(C3)). The operating waveform during this time is
As shown in the figure. to the input signal. and output signal φ. , the time interval τ
is the threshold voltage vth(C4)S value of capacitor C1 and MO
S Determined by the characteristics of the transistor Q2, the time τ becomes longer as the gain constant β (C2) of the MOS transistor C2 becomes smaller or the threshold voltage vtt1 (C2) becomes larger. As for the threshold voltage vth (C4), the larger the value, the shorter the time τ, and the smaller the value of the capacitor C1, the shorter the time τ. Furthermore, MOS)
V is the maximum voltage difference applied between the source and drain of transistor Q2. Then v. -vDD-vth(Ql)
The voltage difference is given between the nodes NL and NH2.

In the conventional semiconductor integrated circuit of this type, β(C2)l■, h(
C4) Since each value of IC was determined at the time of manufacture and did not change thereafter, the time from the start to the completion of a given circuit operation, that is, τ in the example of Fig. 1, was constant. However, this had the disadvantage that it could not be adjusted after manufacturing.

The present invention has been made in order to solve the above-mentioned drawbacks. The device is characterized in that it is configured such that a high voltage can be applied to the specific MOS transistor during the period of 1.

The drawings will be explained in detail below.

FIG. 3 shows an embodiment of the present invention, in which 1 is a switch circuit;
NH and NH2 are two nodes to which a voltage difference vH larger than vvo is applied, and terminals P3 and P4 are connected to a power source with a voltage of -, and the other parts are the same as in FIG. As for the operation of this circuit, first consider the case where the switch circuit 1 connects the drain of the transistor Q2 to the node NL1, the source to the node NL2, and the gate to the input signal φin (D) in the normal mode. It is clear that this situation is similar to the case described in the conventional example shown in FIG.

Next, the operation in the adjustment mode, which is a feature of the present invention, will be explained. This adjustment mode is for setting the characteristics of a specific MOS transistor (2 in this embodiment) in the integrated circuit to a desired specific value during any period other than the above-mentioned normal mode period. In this adjustment mode, the drain of the MOS transistor Q is connected to the node NH, the source is connected to the node 2, and the gate is connected to the node NH by the switch circuit 1.
□ and V between the drain and source of transistor Q2. When a large voltage difference is applied, the MOS transistor Q2 becomes conductive and current flows. At this time, in a MOS transistor, hot carriers are injected into the gate oxide film (hereinafter referred to as a hot carrier phenomenon), and the characteristics of the MOS transistor change. In the case of an N-channel MOS transistor, what corresponds to carriers are electrons, and the direction of change in characteristics is a direction in which the gain constant becomes smaller and a direction in which the threshold voltage becomes larger. Further, the amount of change increases as the time period during which the MOS transistor is conductive due to the high voltage applied between the source and drain increases. Therefore, in the embodiment of FIG. 3, by switching to the adjustment mode by the switch circuit 1,
It is possible to decrease the gain constant β(C2) of the transistor Q2 and increase the threshold voltage vth(C2) of the transistor Q2. That is, the discharge time constant of the capacitor C1 in the normal mode can be changed in the direction of increasing the input signal φin and the output signal φ. The time interval of ut can be adjusted.

Note that the ease with which the true carrier phenomenon occurs depends on the effective channel length of the MOS transistor and the magnitude of the voltage applied between the source and drain. For example, in an N-channel MOS transistor with an effective channel length of around 1 μm, changes in characteristics due to hot carrier phenomena are negligible even if the transistor is kept conductive for more than 10 years at an applied voltage of 5 V or less. . On the other hand, when the applied voltage to the same MOS transistor is increased to IOV or more, the gain constant decreases by several orders of magnitude or more even if the conduction state continues for just a few seconds.
Generally, a threshold voltage increase of 0 mV or more occurs and this state continues. Therefore, in the embodiment of Fig. 3, vDD-5v
Considering the case, Vo= 5% (Q,) <
Since it is 5V, it is a MOS transistor. By setting the effective channel length of 2 to about 1 μm and selecting the threshold voltage vH near IOV, a semiconductor integrated circuit that can be adjusted at time intervals even after manufacturing is realized.

Also, the above time interval τ can be adjusted using a MOS transistor. This is an adjustment in the direction of lengthening the time interval τ by changing the characteristics of MOS transistor Q4.
In the adjustment mode, the threshold voltage v
th(C4) can be increased), adjustment in the direction of shortening the time interval can also be easily realized.

There are no particular restrictions on how to configure the switch circuit, but if a MOS transistor is used as the switch element of the switch circuit, the effective channel length of the MOS transistor should be longer than the effective channel length of the MOS transistor Q2 or C4. It is desirable to reduce the influence of the hot carrier phenomenon on the MOS transistors in the switch circuit by increasing the drying time. Alternatively, in the adjustment mode, it is not always necessary to disconnect the MOS transistors whose characteristics are to be changed from the nodes NL, NL2, so the nodes NL and Nb2 are connected to the nodes NH and NL2 respectively.
,,configuration to remain connected to NH2 and no configuration, terminal P3
．． It is also possible to enter the adjustment mode by applying the threshold voltage YH between P4.

If this adjustment mode only needs to be used for a period of time after manufacturing, for example during wafer probing, terminals P3tP4 can simply be provided as pads within the semiconductor integrated circuit, and neither a switch circuit nor bonding of the casing is necessary.

It is also possible to configure one of the terminals P3 and P4 to be shared with one of the power supply terminals P1 and P2. In short, it is sufficient to have a configuration in which a high voltage is applied to a specific MOS transistor for a certain period of time, and various modifications and changes can be made without departing from the spirit of the present invention.

Next, a method for generating high voltage used in the adjustment mode within a semiconductor integrated circuit will be described. Figure 4 shows an example, where 2 is an oscillation circuit, C2 is a capacitor, and C2 is an oscillation circuit.
5 and C6 are MOS transistors. capacitor c
One end of the oscillation circuit 2 is connected to the output terminal of the oscillation circuit 2, and the other end is connected to the source of the transistor Q and the drain of the MOS transistor Q6.

The drain of the MOS transistor Q5 is connected to the power supply terminal P1. In the example of FIG. 4, a high voltage difference vH' occurs between the source of the MOS transistor Q6 and the power supply terminal P2.
If configured to be used as H, l NH2, the voltage v
This makes it possible to eliminate the need for an external power source.

Note that the voltage amplitude at the oscillation circuit output terminal is vO8e', and the voltage between terminal P and P2 is V. If D, then 1′≦VDD
+■osc, vth (C5) -vth (C6
). Furthermore, it goes without saying that the KMOS transistors Q5 and C6 may be replaced with diodes.

The configuration in this case is shown in FIG.

Further, in the description of the above embodiment, adjustment of the time interval τ was described, but this applies only to MOS transistors. Regarding 3, MOS transistor. If a switch circuit similar to that for 2 is added, the output signal φ. . It is also possible to adjust the slope at the rise of .

As explained above, since the structure is such that the gain constant and threshold voltage of the MOS transistor in the semiconductor integrated circuit can be changed even after manufacturing, the predetermined circuit operation of the semiconductor integrated circuit is completed after it starts. In particular, when the present invention is applied to a large-scale integrated circuit equipped with a large number of clock generation circuits, the time margin between the clocks can be adjusted, and the time margin between the clocks can be adjusted. It has the advantage that it can be finely adjusted later and that a high-performance semiconductor integrated circuit can be easily realized.

[Brief explanation of drawings]

Fig. 1 is an example of a conventional semiconductor integrated circuit, Fig. 2 is an operating waveform of a conventional semiconductor integrated circuit, Fig. 1JK3 is an example of a semiconductor integrated circuit according to the present invention, and Fig. 4 is used in a semiconductor integrated circuit according to the present invention. A first example of a high voltage generating circuit, and FIG. 5 similarly shows a second example. 1...Switch circuit, 2...
...Oscillation circuit, Q1 to Q6...MO
S) Transistor, C1, C2... Capacitor, P□~P4... Song power terminal, NL,...
NL2. NH,l NH2・・・・・・Node,
φ, ...... precharge signal, φ
・A: Input signal, φ. 0.・・・n ・・・・・・Output signal, Dl, D2・・・・・・・・・
diode. Fig. 1 Fig. 2 NL+f)

Claims (1)

[Claims] In a semiconductor integrated circuit having a plurality of MOS transistors and for performing a predetermined circuit operation, the plurality of M
In order to adjust the characteristics of a certain MOS transistor (such as Q2) in a certain MOS transistor (OS) transistor, a voltage is applied between the source and the ton-in of that particular MOS transistor during the period of the predetermined circuit operation. 1. A semiconductor integrated circuit comprising means for applying a voltage difference (vH) larger than a maximum voltage difference (vo) between the two during any period other than the period during which the predetermined circuit operation is performed.