JPS58115513A - Frequency variable microcomputer - Google Patents

Abstract

PURPOSE:To reduce the power consumption, by supplying clocks of a frequency matched to the operation mode of a processing circuit to the processing circuit to operate it. CONSTITUTION:When a microcomputer enters into a high-speed operation mode of the normal operation, a prescribed instruction code is set to an idle register 6. Contents of this code are decoded by a decoder 7, and a high-level signal is generated on a line 8 and is applied to an AND circuit 3. High-speed clocks obtained by dividing a frequency (f) from an oscillator 1 to f/n in a frequency divider 2 are supplied from the circuit 3 to an internal processing circuit of the computer through an OR circuit 13. When the processing in the high-speed mode is terminated and the device enters into the idle state, a corresponding instruction code is set to the register 6. Contents of this code are decoded by the decoder 7, and a high-level signal is generated on a line 9 and is applied to an AND circuit 4. The circuit 4 outputs low-speed clocks obtained by dividing the frequency (f) to f/m in the frequency divider 2, the these clocks are supplied to the processing device through the circuit 13. Since the power consumption of the processing device constituted with a CMOS is dependent upon the operating frequency, the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a variable frequency mw microcombinator which is operated at a frequency tarok according to the amount of processing required.

(3) Background of the technology In microcomputers in which arithmetic circuits and various registers are integrated on a single semiconductor substrate, the clock used for its operation has a high frequency of 18 to increase its operating speed. However, there are some processes that do not necessarily need to operate with such a high frequency clock. For example, when a microcomputer is used in a device such as a putukuyuphone, the amount of information processed by the microcomputer increases when it is in the hook-off state. No clock frequency is required.

Therefore, when performing such processing, there is a growing demand for lower power consumption.

(3) Prior Art and Problems Among the conventional microcomviators, there is a microcomputer using 4CFiCMO8. Such computers and the like are configured to operate with a clock of a predetermined frequency regardless of the processing content. Therefore, the power consumption remains constant regardless of the processing content, and within this limit, it is impossible to achieve a reduction in power consumption.

(4) 1. Purpose of the Invention The present invention was devised by focusing on the drawbacks of the conventional device as described above, and its purpose is to provide a frequency-enabled microcomputer that can reduce power consumption. .

(5) Configuration of the Invention This object is achieved by supplying a clock of a frequency corresponding to the operating mode of the processing circuit whose power consumption is dependent on the operating frequency to the processing circuit to operate it.

(6) First Embodiment of the Invention Hereinafter, embodiments of the present invention will be explained with reference to the accompanying drawings.

The accompanying drawing shows a clock generation circuit that supplies a clock to a microcomputer. In the figure, reference numeral 1 denotes an oscillation circuit that generates a signal of frequency f, and its output is connected to the input of a frequency dividing circuit 2.

The two frequency dividing circuits each have at least two frequency divided outputs.

Of these frequency-divided outputs, for example, the output of f/ is connected to one input of the AND circuit 3, and the output of f/m is connected to one input of the AND circuit 4. Here, m>n
The output of t't%f/n is used as a high-speed clock, and the output of 7jf/m is used as a low-speed clock.

The other input of the AND circuit 3.4 is supplied with signals from the operation mode determination circuit 5 separately. That is, a decoder 7 is connected to the output of the idle register 6 in which the operating mode is set in terms of hardware and welfare 7F, and a display signal for each operating mode is generated from the decoder. For example, if the microcomputer is in a high-speed operating mode, i.e., normal operation of the microcomputer, a high level signal is generated on the line 8 connected to the other input of the AND circuit 3, and a low-speed operating mode, i.e., the microcomputer is in standby. , a high level signal is generated on line 9 connected to the other input of AND circuit 4. Line 10 connected to register 6 is the ninth line of the signal that causes its reset. 11 is a signal line that sets register 6 in terms of hardware, 1
This is the line for setting register 6 in the software of the two companies.

The output of the AND circuits 3 and 4 is the input 5II+ of the OR circuit 13
The output of the OR circuit 13 becomes the clock of the microcomputer.

The operation of the computer of the present invention having the above-mentioned configuration will be explained.

For convenience of explanation, the commercial for the processing circuit of a microcomputer
It is assumed that it is composed of O1l.

When the microcomputer enters a normal operation mode, that is, a high-speed operation mode, a predetermined instruction code is set in the idle register 6. Its contents are decoded by decoder 7 and a high level output signal is generated on line 8, thereby causing the signal of oscillator 1, divided by 112 times 112, from oscillator 1 to the high speed clock. The signal passes through the AND circuit 3 and is supplied via the OR circuit 13 to the processing circuit of the micro convenience store s, which is operated by the f/n ratio p.

When processing in such a high-speed mode is completed and the device enters a standby state, that is, an idle state, an instruction code to that effect is set in the idle register 6. A high level signal is generated on line 9 from decoder 7 which decodes its contents.

As a result, the f/m frequency signal of the frequency divider circuit 2 passes through the AND circuit 4, passes through the OR circuit 13, and then passes through the 0 MO
8 and operates it in a low speed mode.

By the way, the power consumption P of 0MO8 is also PcmCCIVc f1+c2V%ef2-)--
・There is a relationship expressed by . However, in the above formula, C1, C.

is a constant, VacFiCMO8 (D operating voltage, fl, f,
, -... are each frequency of the clock.

Therefore, as mentioned above, if the processing circuit configured with 0MO8 is operated with a low-speed clock in the standby state that is taken after the normal operation of the high-speed clock ends, then as is clear from the above equation, , it is possible to operate with reduced power consumption in the processing circuit. This effect is particularly advantageous when the standby state is frequently used or the standby state is opened for a relatively long time.

Such a reduction in power consumption is also advantageous in terms of heat dissipation measures for the device.

Although the above embodiment has been described with the frequency division of the frequency dividing circuit fixed, it goes without saying that the ratio of n7m may be configured to be programmable by the user.

Also, in this embodiment, two types of clocks are switched, but more clocks may be switched, and the setting and resetting of the idle register can be done by software or external hardware interrupts. You can also do this by

Furthermore, the configuration shown in the figure may be integrated into a microcomputer with 111 chips.

(7) 1. More than the effect of 0 invention. As is clear from the description, according to the present invention, when the device enters the standby state, the microcomputer is operated with a clock of a low tIJt number to achieve a reduction in power consumption. This becomes especially noticeable when the duration of Fi is long or when Fi occurs frequently.

The more power consumption is reduced in this way, the more advantageous the cape will be in terms of heat dissipation measures.

[Brief explanation of drawings]

The accompanying drawing is a diagram showing a circuit that generates a clock according to the processing content of the information processing device. In the diagram! 2 is an oscillator, 2 is an I7Id circuit, 3.4 is an AND circuit, 5 is an operation mode determination circuit, and 11 is an OR circuit. Patent applicant Fujitsu Limited Shiri・

Claims (1)

[Scope of Claims] l) A frequency adjustable m-q microcomputer, characterized in that the crotter frequency supplied to the scissors microphone p-computer is switched according to the amount of processing required by the microcombinator Kll'. 2) The switching of the tarock frequency is carried out by setting a predetermined command in a register in the micro combinator circuit by a program. Variable number microcomputer.