JPS58114465A - High molecular semiconductor field effect transistor and manufacture thereof - Google Patents
High molecular semiconductor field effect transistor and manufacture thereofInfo
- Publication number
- JPS58114465A JPS58114465A JP56214985A JP21498581A JPS58114465A JP S58114465 A JPS58114465 A JP S58114465A JP 56214985 A JP56214985 A JP 56214985A JP 21498581 A JP21498581 A JP 21498581A JP S58114465 A JPS58114465 A JP S58114465A
- Authority
- JP
- Japan
- Prior art keywords
- polymer semiconductor
- film
- field effect
- effect transistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 230000005669 field effect Effects 0.000 title claims description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 229920000642 polymer Polymers 0.000 claims description 54
- 238000000034 method Methods 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000005507 spraying Methods 0.000 claims description 4
- 238000006116 polymerization reaction Methods 0.000 claims description 3
- 239000012808 vapor phase Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 229920001197 polyacetylene Polymers 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000005357 flat glass Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 229910052738 indium Inorganic materials 0.000 abstract 1
- 239000002120 nanofilm Substances 0.000 abstract 1
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical class CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 6
- 229920000015 polydiacetylene Polymers 0.000 description 6
- 229920000265 Polyparaphenylene Polymers 0.000 description 4
- 229920006254 polymer film Polymers 0.000 description 4
- -1 polyparaphenylene Polymers 0.000 description 4
- 239000003054 catalyst Substances 0.000 description 3
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000178 monomer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- LLCSWKVOHICRDD-UHFFFAOYSA-N buta-1,3-diyne Chemical group C#CC#C LLCSWKVOHICRDD-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000003595 mist Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 239000002841 Lewis acid Substances 0.000 description 1
- 101500021084 Locusta migratoria 5 kDa peptide Proteins 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 150000001340 alkali metals Chemical class 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- WHVXVDDUYCELKP-UHFFFAOYSA-N butatriene Chemical compound C=C=C=C WHVXVDDUYCELKP-UHFFFAOYSA-N 0.000 description 1
- 229920000547 conjugated polymer Polymers 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052809 inorganic oxide Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000007517 lewis acids Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 150000003242 quaternary ammonium salts Chemical class 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/10—Organic polymers or oligomers
- H10K85/141—Organic polymers or oligomers comprising aliphatic or olefinic chains, e.g. poly N-vinylcarbazol, PVC or PTFE
- H10K85/143—Polyacetylene; Derivatives thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、電界効果トランジスタの改良6二関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in field effect transistors.
従来、電界効果トランジスタは、半導体としてシリコン
、ゲルマニウム等の無機半導体を使用している。一般覗
;、無機半導体は結晶の引上装置。Conventionally, field effect transistors have used inorganic semiconductors such as silicon and germanium as semiconductors. General view: Inorganic semiconductors are crystal pulling devices.
エピタキシャルfit等の寸法によりその面積が限定さ
れてしまい、例えば単結晶シリコンでは現在約15Cy
a(6インf)径程度のものしかできない。Its area is limited by the dimensions of the epitaxial fit, etc., and for example, in single crystal silicon, it is currently about 15 Cy.
Only a diameter of about a (6 inches f) can be produced.
それ故、電界効果トランジスタを大面積の基板上で形成
することができない欠点がある。又、無機半導体は本質
的C二可撓性、成型性および低価格性等砿二麹があるの
で、これを使用する従来の電界効果トランジスタもこの
ような面での制約を受けていた。Therefore, there is a drawback that a field effect transistor cannot be formed on a large-area substrate. Furthermore, since inorganic semiconductors inherently have characteristics such as flexibility, moldability, and low cost, conventional field effect transistors using them have also been subject to limitations in these respects.
本発明はこのような従来の欠点を改善したものであり、
その目的は、半導体として高分子半導体を使用すること
(二より可撓性、成型性、低価格性等≦二優れた大面積
化の容易な電界効果トランジスタ及びその製造方法を提
供すること(二ある。以下実施例(二ついて詳細に説明
する。The present invention improves these conventional drawbacks, and
The purpose is to use a polymer semiconductor as a semiconductor (2) to provide a field effect transistor with excellent flexibility, moldability, low cost, etc. (2), which can easily be made into a large area, and a method for manufacturing the same (2). There are two examples below, which will be explained in detail.
第1図は本発明の一実施例であるショットキーパリアゲ
ート電界効果トランジスタの素子断面図であり、11は
絶縁基板、12は高分子半導体膜、16はショットキー
バリアを形成するゲート電極(ゲート被膜)、14 、
15はオーミック接触を有するソース電極及びドレイン
電極である。FIG. 1 is a cross-sectional view of a Schottky barrier gate field effect transistor according to an embodiment of the present invention, in which 11 is an insulating substrate, 12 is a polymer semiconductor film, and 16 is a gate electrode (gate film) forming a Schottky barrier. ), 14,
15 is a source electrode and a drain electrode having ohmic contact.
本実施例は、絶縁基板11上(二高分子半導体膜12を
重合により形成し、その上6二ゲート電極15を形成し
、ゲート電極15直下のゲート領域を間シスした高分子
半導体膜12上ロソース電極14及びドレイン電極15
を形成したものである。In this embodiment, a two-polymer semiconductor film 12 is formed by polymerization on an insulating substrate 11, two gate electrodes 15 are formed thereon, and a gate region directly below the gate electrode 15 is disposed on the polymer semiconductor film 12. Low source electrode 14 and drain electrode 15
was formed.
高分子半導体1[12としてP型の高分子半導体を使用
した場合、ゲート電極13は、ショットキーバリアを得
る為に仕事関数の小さな材質、例えばAl 、 If&
、 My等を使用する。また、高分子半導体膜12とし
て筒型の高分子半導体を使用する場合6吋よ、仕事関数
の大きな材質、例えばPt 、 Aμ等でゲート電極1
3を構成する。ソース電極14.ドレイン電極15はP
型2%型のいずれの場合でも、オーミックコンタクトが
可能な金属や高導電率の半導体を用いれば良い。絶縁基
板11としては、板ガラス。When a P-type polymer semiconductor is used as the polymer semiconductor 1[12, the gate electrode 13 is made of a material with a small work function, such as Al, If&
, My, etc. are used. In addition, if a cylindrical polymer semiconductor is used as the polymer semiconductor film 12, the gate electrode 1 should be made of a material with a large work function, such as Pt or Aμ.
3. Source electrode 14. The drain electrode 15 is P
In either case of the 2% type, a metal or a semiconductor with high conductivity that allows ohmic contact may be used. The insulating substrate 11 is plate glass.
表面酸化処理シリコンウェハー、高分子フィルム等を使
用できる。Surface oxidized silicon wafers, polymer films, etc. can be used.
一般Cニゲート幅は長い程良く、100μ講〜5xgt
x程度(;する。゛一方ゲート長、即ちソース、ドレイ
ン間隔は短い程好ましく、50μm〜1μ寡の間程度C
二する。同図の電極配置は、高分子半導体膜12の片面
のみ使用するコプレーナ構造9両面を使用するスタガ構
造ζニすることが可能である。以下、このショットキー
バリアゲート電界効果トランジスタのより具体的な実施
例について説明する。Generally, the longer the width of the C gate, the better, 100μ ~ 5xgt
On the other hand, the gate length, that is, the distance between the source and drain, is preferably as short as possible.
Two. The electrode arrangement in the figure can be a coplanar structure in which only one side of the polymer semiconductor film 12 is used, and a staggered structure in which both sides of the polymer semiconductor film 9 are used. A more specific example of this Schottky barrier gate field effect transistor will be described below.
具体例1
絶縁基板11として50冨雇xso扉屏x1mm(厚さ
)のガラス基板を用い、この上(二AZ1550J(商
品名)レジストを塗布し、これを公知のホトリソグラフ
ィ法でパタにングして1yxax1msの正方形の穴を
持つレジストパターンを6個作成した。Specific example 1 A glass substrate of 50 mm x 1 mm (thickness) was used as the insulating substrate 11, and a resist (2 AZ1550J (trade name)) was applied thereon, and this was patterned using a known photolithography method. Six resist patterns each having square holes of 1yxax1ms were created.
次(:、このパターニングされたレジスト上−二t−ダ
ラー触媒(オノノソプトオキシチタンとポリエ:lF−
ルアルミニクムをAX/Ti= 4の比C二なるよう(
二してトルエンでまぜ、Tiベースで濃度100 m
male/1としたもの)をQ、5’ml塗布し、その
後、上記基板を常圧のArガス中に置きアセチレンガス
な5Qcc1分の速度で前記基板に吹き付けた。これに
より、前記基板上(二厚さ0.2μ専のシス型のポリア
セチレン膜が重合形成された。なお、このときデーグラ
−触媒の作用(二より高分子半導体!i12はP型の導
電性となった。更C二導電率を高める為に、P型のドー
パントをドーピングしても良いことは勿論のことである
。Next (:, on this patterned resist-dit-Daller catalyst (ononosoptoxytitanium and polyester: IF-
The ratio of AX/Ti = 4 is C2 (
Then mix with toluene to make a Ti base with a concentration of 100 m
After that, the substrate was placed in Ar gas at normal pressure and acetylene gas was sprayed onto the substrate at a rate of 5Qcc 1 min. As a result, a cis-type polyacetylene film having a thickness of 0.2 μm was polymerized and formed on the substrate. Of course, it is also possible to dope with a P-type dopant in order to further increase the C2 conductivity.
次に、トルエンで基板を5回洗浄してチーグツ−触媒を
除去し、その後、内、王をAデガスで約1.5〜2気圧
程度に加圧した2Qccのア七トン(他のレジスト溶剤
でも良い)を入れたスプレー容器のノズルから霧状の1
七トンを基板ζ二噴霧した。この霧状のアセトンは重合
膜を通してレジストζ二連し、レジストは基板から剥離
した。このとき、レジスト上の重合膜も一緒4=剥離さ
れるので、リフトオフ6:よって基板上には重合膜のパ
ターンが形成された。なお、通常の如くアセトンを単に
塗布或いはアセトン(:浸漬しただけではうまくリフト
オフできなかった。Next, the substrate was washed 5 times with toluene to remove the Tigutsu catalyst, and then the substrate was pressurized to about 1.5 to 2 atm with A degas. Atomized 1 from the nozzle of a spray container containing
Seven tons were sprayed onto two substrates. This acetone mist passed through the polymeric film and connected to the resist ζ, and the resist was peeled off from the substrate. At this time, the polymer film on the resist was also peeled off (4), so a pattern of the polymer film was formed on the substrate (lift-off 6). It should be noted that lift-off could not be achieved successfully by simply applying acetone or dipping it in acetone as usual.
次に、レジストを用いて、幅6000μ扉、長さ5μm
のゲート電極を作成した。この場合、ポリアセチレンは
P型半導体であるため、ゲート電極6ニアルミニクムを
用いた。また、幅3000μ罵のソース電極14及びド
レイン電極15を金を用いて形成した。Next, using resist, a door with a width of 6000 μm and a length of 5 μm was created.
A gate electrode was created. In this case, since polyacetylene is a P-type semiconductor, 6N aluminum was used for the gate electrode. Further, a source electrode 14 and a drain electrode 15 having a width of 3000 μm were formed using gold.
このようにして製造したショットキーゲート型ポリアセ
チレン電界効果トランジスタの伝達特性を第2図(;示
す。同図から判るよう(二、ドレイン電圧10Vでym
がほぼ100μ哲を示し、周波数特性の1つである遮断
周波数f、は1KHzを示した。また、第3図はその出
力特性の一例を示す線区である。The transfer characteristics of the Schottky gate type polyacetylene field effect transistor manufactured in this way are shown in Figure 2.
was approximately 100μ, and the cutoff frequency f, which is one of the frequency characteristics, was 1KHz. Moreover, FIG. 3 is a line section showing an example of the output characteristics.
具体例2
この実施例は高分子半導体としてブタトリエン型ポリジ
しセチレンを用いたものである。Specific Example 2 In this example, butatriene type polyamide and cetlene was used as the polymer semiconductor.
Jl子半導体膜12は、ジアセチレンモノマーを絶縁基
板11上に膜状(二形成し、これ!=180Mrad/
hrのガンマ線を100時間照射して膜厚0.1μ専の
ポリジアセチレンフィルムとした。なお、この時ジアセ
チレンモノマーCニヨウ素等をドーピングしておいても
良い。そして他のパラメータを具体例1と同じにしてシ
ョットキーバリアゲート型ポリジアセチレン電界効果ト
ランジスタを製造した。The secondary semiconductor film 12 is formed by forming a film of diacetylene monomer on the insulating substrate 11, and this ! = 180 Mrad/
A polydiacetylene film having a thickness of 0.1 μm was obtained by irradiating with gamma rays for 100 hours. Note that at this time, diacetylene monomer C, niiodine, etc. may be doped. Then, a Schottky barrier gate type polydiacetylene field effect transistor was manufactured using the same parameters as in Example 1.
この結果、ymがほぼ1簿25(ドレイン電圧ろ=10
m’)、f、がほば100 KHzを示す電界効果トラ
ンジスタが得られた。As a result, ym is approximately 1.25 (drain voltage = 10
A field effect transistor was obtained in which m') and f were approximately 100 KHz.
第4図は本発明の別の実施例であるゲートと半導体の間
C二絶縁膜を持つMIS型電界効果トランジスタの素子
断面図であり、第1因と同一符号は同一部分を示し、1
6はグー)電極、17は絶縁膜である。FIG. 4 is a cross-sectional view of a MIS type field effect transistor having a C2 insulating film between the gate and the semiconductor, which is another embodiment of the present invention.
6 is a goo electrode, and 17 is an insulating film.
本実施例は、絶縁基板11上に形成したゲート電極16
上に絶縁膜17を形成し、この絶縁膜17上ζ二高分子
半導体1[i2を重合形成し、ゲート領域を間にした高
分子半導体膜12上(二ソース電極14及びドレイン電
極15を形成したものである。In this embodiment, a gate electrode 16 formed on an insulating substrate 11 is used.
An insulating film 17 is formed on the insulating film 17, and a ζ bipolymer semiconductor 1[i2 is polymerized and formed on the insulating film 17, and a source electrode 14 and a drain electrode 15 are formed on the polymer semiconductor film 12 with the gate region in between. This is what I did.
ゲート電極16はいずれの金属で構成しても良いが、ソ
ース電極14及びドレイン電極15は高分子半導体膜1
2とオーミック接触し得る材質である必要がある。絶縁
膜17としては、プラズマ重合膜、熱分解気相重合膜(
例えばパリレン膜(商品名))、無機酸化物膜等を使用
できる。ゲート幅、ゲート長等のトランジスタの大きさ
は、第1図のショットキーパリアゲート電界効果トラン
ジスタと同様である。トランジスタ構造としては、高分
子半導体膜12の片面のみに電極を構成するコプレーナ
構造及び両面≦二電極を構成するスタガ構造にすること
が可能である。以下、このMIS型電界効果トランジス
タのより具体的な実施例(二ついて説明する。The gate electrode 16 may be made of any metal, but the source electrode 14 and drain electrode 15 are made of the polymer semiconductor film 1.
The material must be able to make ohmic contact with 2. As the insulating film 17, a plasma polymerized film, a pyrolytic vapor phase polymerized film (
For example, a parylene film (trade name), an inorganic oxide film, etc. can be used. The dimensions of the transistor, such as gate width and gate length, are the same as the Schottky pariah gate field effect transistor shown in FIG. The transistor structure can be a coplanar structure in which an electrode is formed on only one side of the polymer semiconductor film 12, or a staggered structure in which both sides are formed with two electrodes. Hereinafter, two more specific embodiments of this MIS field effect transistor will be explained.
具体例6
絶縁基板11としてガラス基板を用い、この上にアルミ
ニクムを蒸着し次いでパターニングしてゲート長1μ唇
、ゲート幅5000μmのゲート電極16を形成した。Specific Example 6 A glass substrate was used as the insulating substrate 11, and aluminum was deposited thereon and then patterned to form a gate electrode 16 having a gate length of 1 μm and a gate width of 5000 μm.
次に、絶縁膜17として、オルガノシロキチンをモノマ
ーとする膜厚500Aのプラズマ重合膜なグー)’ti
t(極16上と二形成した。このプラズマ重合膜による
ゲート電極の形成C二は、前述したレジスト溶剤の加圧
スプレーとリフトオフ法を使用するのが有効である。ゲ
ート電極16C;熱分解気相重合膜を用いた場合も同様
である。Next, as the insulating film 17, a plasma polymerized film with a film thickness of 500 A containing organosylochitin as a monomer is used.
t (2 formed on the electrode 16. Formation of the gate electrode C2 using this plasma polymerized film is effective by using the above-mentioned pressurized spraying of resist solvent and lift-off method. Gate electrode 16C; pyrolysis gas The same applies to the case where a phase polymer film is used.
次に、絶縁膜17上C:高分子半導体膜12として厚さ
200OAのボ9アセチレン膜を直接重合C二より形成
した。この場合も上記スプレー法とリフトオフ法を使用
するのが有効である。そして、その上(二金から成るソ
ース電極14及びドレイン電極15をソース・ドレイン
間隔1μ専で形成した。Next, C: on the insulating film 17: A Bo9 acetylene film having a thickness of 200 OA was formed as the polymer semiconductor film 12 by direct polymerization C2. In this case as well, it is effective to use the above-mentioned spray method and lift-off method. Then, on top of that, a source electrode 14 and a drain electrode 15 made of dimetallic metal were formed with a source-drain spacing of 1 μm.
このようζ二して製造したMXS型ポリアセチレン電界
効果トランジスタの伝達特性を第5図C;示す。The transfer characteristics of the MXS type polyacetylene field effect transistor manufactured in this way are shown in FIG. 5C.
ドレイン電圧VD=10VでgTn、jSはば1−5m
?!;、fr= 10 KHzを示した。また、第6図
(−その出力特性の一例を示す。When the drain voltage VD=10V, gTn and jS are 1-5m.
? ! ;, showed fr=10 KHz. Moreover, FIG. 6 (-- shows an example of its output characteristics.
具体例4
高分子半導体膜12として黒体例2で使用したポリジア
セチレンを用い、膜厚を0.2μ屏とした以外他のトラ
ンジスタ構造パラメータを具体例3と同じにしたMIS
型ポリジアセチレン電界効果トランジスタを作成した。Specific example 4 MIS using the same polydiacetylene used in black body example 2 as the polymer semiconductor film 12 and using the same transistor structure parameters as specific example 3 except that the film thickness was set to 0.2 μm.
A type polydiacetylene field effect transistor was fabricated.
その結果、ドレイン電流1゜は減少したが、ドレイン電
圧V、 = i 0 Vでの!扉は3講υと大きくなっ
た。また、f、は15D KHzであった。As a result, the drain current decreased by 1°, but the drain voltage V, = i 0 V! The door became larger by 3 doors. Further, f was 15D KHz.
具体例5
絶縁w/X17としてスパッタ法で形成した厚さ500
λのAI、 Osを使用した以外具体例4と同じC二し
たMIS型電界効果トランジスタを製造したところ、ド
レイン電圧Vn = 10 Vでgm= j a23、
fr = 70KHzのトランジスタが得られた。Specific example 5 Insulation w/X17 with a thickness of 500 mm formed by sputtering
When a MIS type field effect transistor with C2, which is the same as in Example 4 except that AI and Os of λ were used, the drain voltage Vn = 10 V and gm = j a23,
A transistor with fr = 70 KHz was obtained.
第7図は、本発明の電界効果トランジスタに使用できる
高分子半導体の分子構造を示す因であり、(1)はトラ
ンス型ポリアセtレン、(2)はシス型ポリアセチレン
、(3)はポリピロール、(4)はポリチェニレン、(
5)はポリパラフェニレン、(6)はポリパラフェニレ
ンビニレ:/、(7)はポリパラフェニレンスルフィド
、(8)はポリパラフェニレンオキシド、(9)はアセ
チレン型ポリジアセチレン、(1のはブタトリエン型ポ
リジアセチレンをそれぞれ示す。一般に、高分子半導体
としては直鎖状共役系高分子が優れた半導体特性を示す
。第6図は、直接膜状(二重合できるそのような直鎖状
共役系高分子半導体の分子構造を示したものである。本
発明はこの他に、半導体特性を示す高分子を使用するこ
とが可能である。なお、高分子半導体を電流方向C鎖状
が伸びる構造とすれば、電気特性は良くなる。FIG. 7 shows the molecular structures of polymer semiconductors that can be used in the field effect transistor of the present invention, in which (1) is trans-type polyacetylene, (2) is cis-type polyacetylene, (3) is polypyrrole, (4) is polythenylene, (
5) is polyparaphenylene, (6) is polyparaphenylene vinyl:/, (7) is polyparaphenylene sulfide, (8) is polyparaphenylene oxide, (9) is acetylene type polydiacetylene, (1 is Butatriene-type polydiacetylenes are shown respectively.In general, linear conjugated polymers exhibit excellent semiconductor properties as polymer semiconductors. This figure shows the molecular structure of a polymer semiconductor.In addition to the above, the present invention can also use polymers that exhibit semiconducting properties.The polymer semiconductor can be constructed with a C chain extending in the current direction. This will improve the electrical characteristics.
第6図&:示した高分子半導体は不純物(ドーパント)
としてへログン又はルイス酸を添加する(ドープする)
ことでP型半導体とすることができ、アルカリ金属又は
四級アンモニウム塩をドープすることでル型半導体とす
ることができる。又、電気伝導度の増加も認められる。Figure 6 &: The polymer semiconductor shown is an impurity (dopant)
Add (dope) helogne or Lewis acid as
By doping with an alkali metal or quaternary ammonium salt, a P-type semiconductor can be obtained. An increase in electrical conductivity was also observed.
よって、前述の如く無機半導体と同じようζ二半導体デ
バイスとして用いることが可能となる。Therefore, as described above, it can be used as a ζ2 semiconductor device in the same way as an inorganic semiconductor.
なお、第1図及び第4図C二おけるソース電極14及び
ドレイン電極15或いは第4図におけるゲート電極16
としては、前述したも、の以外(二、高分子半導体にヨ
ク素、へロゲン等を気相拡散等で拡散して不純物のドー
ピングを行い、低抵抗化したものを使用しても良い。ま
た、絶縁基板11としても、高分子半導体の二重結合を
断ち切って絶縁化したものを用いることができる。Note that the source electrode 14 and the drain electrode 15 in FIGS. 1 and 4C2 or the gate electrode 16 in FIG.
In addition to the above, (2) a polymer semiconductor may be doped with impurities by diffusing iodine, herogen, etc. by vapor phase diffusion, etc. to lower the resistance. Also, as the insulating substrate 11, a polymer semiconductor insulated by breaking the double bonds can be used.
以上の説明から判るように、本発明(=よれば、半導体
に高分子半導体を使用しているので、可撓性、成型性、
低価格性等に優れた大面積化の容易な電界効果トランジ
スタが容易(二重られる効果がある。As can be seen from the above explanation, the present invention (=) uses a polymer semiconductor as a semiconductor, so it has flexibility, moldability,
It is easy to create field effect transistors that are low cost and easy to increase in area (there is a double effect).
即ち、高分子半導体では、大面積の基板上(二触媒を塗
布しその後原料ガスを基板上(二導入する方法を用いる
ことができるので、無機半導体の如く結晶の引上装置、
エピタキシャル成長装置等の装置による制約を受けずζ
二人面積の基板上(二素子を形成できるものである。That is, in the case of polymer semiconductors, it is possible to use a method in which a catalyst is coated on a large-area substrate (two), and then raw material gas is introduced onto the substrate (two), so it is possible to use a crystal pulling device like inorganic semiconductors.
Not limited by equipment such as epitaxial growth equipmentζ
On a substrate with an area of 2 people (2 elements can be formed).
また基板として可撓性のものを用い、更に電極としても
可撓性の材料、例えば高分子半導体に不純物をドーピン
グしその導電率を高めたものを用いれば、高分子半導体
自体が可撓性を持つので、可撓性のある素子を実現でき
るものとなる。このような可撓性のある素子を用いれば
、曲面上(二素子を形成できるので、基板ごと丸めるよ
うにすれば空間を有効に利用でき、素子密度を向上する
ことができる。Furthermore, if a flexible substrate is used and a flexible material is used as the electrode, for example, a polymer semiconductor doped with impurities to increase its conductivity, the polymer semiconductor itself becomes flexible. This makes it possible to realize a flexible element. If such a flexible element is used, two elements can be formed on a curved surface, so if the entire board is rolled up, space can be used effectively and element density can be improved.
更に、大面積を有する高分子半導体を一括成型で形成で
き、また所望の形状の高分子半導体をリングラフィ技術
を用いずi;形成できるので、その成型性が向上する。Furthermore, since a polymer semiconductor having a large area can be formed by batch molding, and a polymer semiconductor having a desired shape can be formed without using phosphorography technology, its moldability is improved.
また高分子材料自体が低価格なので、無機半導体材料を
用いる場合≦二元べ低価格な素子を提供できることにな
る。更(二、製造工程中の最高温度は、レジストをプリ
ベークする際の約90℃であり、低温プロセスに最適で
ある。Moreover, since the polymer material itself is low in price, when an inorganic semiconductor material is used, it is possible to provide an element that is low in cost. Furthermore, the maximum temperature during the manufacturing process is approximately 90° C. when prebaking the resist, which is optimal for low-temperature processes.
従って、本発明の高分子半導体電界効果トランジスタを
大型表示用ドライバーデバイス、大面積集積回路2曲面
構造体への一体回路等に適用すれば非常i二有効である
。Therefore, it is extremely effective to apply the polymer semiconductor field effect transistor of the present invention to large-sized display driver devices, large-area integrated circuits integrated into two-curved structures, and the like.
また、高分子半導体電界効果トランジスタの高分子半導
体を使用した膜をリフトオフ法により形成する@4二、
スプレーでレジスト溶剤を霧状(=噴霧すれば容易にリ
フトオフすることができる。In addition, @42, which forms a film using a polymer semiconductor of a polymer semiconductor field effect transistor by a lift-off method,
Lift-off can be easily achieved by spraying the resist solvent in a mist form (=spraying).
第1図は本発明の一実施例であるショットキーバリアゲ
ート電界効果トランジスタの素子断面図、WI2図及び
第5図はショットキーバリアゲートポリアセチレン電界
効果トランジスタの伝達特性及び出力特性の一例を示す
線図、第4因は本発明の別の実施例であるゲートと半導
体の間(=絶縁膜をスタの伝達特性及び出力特性の一例
を示す線図、第7図は、本発明の電界効果トランジスタ
に使用できる高分子半導体の分子構造を示す図である。
11は絶縁基板、12は高分子半導体膜、13はショッ
トキーバリアを形成するゲート電極、14はソース電極
、15はドレイン電極、16はゲート電極、17は絶縁
膜である。
第1図
第2 図
vo(ボルト)
第40
第5図
第611i5
VD(ボルト)Figure 1 is a cross-sectional view of a Schottky barrier gate field effect transistor according to an embodiment of the present invention, and Figures WI2 and 5 are lines showing examples of transfer characteristics and output characteristics of a Schottky barrier gate polyacetylene field effect transistor. The fourth factor is another embodiment of the present invention, which is a diagram showing an example of the transfer characteristics and output characteristics of the gate and semiconductor (= insulating film), and FIG. 7 is a field effect transistor of the present invention. 11 is a diagram showing the molecular structure of a polymer semiconductor that can be used for. 11 is an insulating substrate, 12 is a polymer semiconductor film, 13 is a gate electrode forming a Schottky barrier, 14 is a source electrode, 15 is a drain electrode, and 16 is a The gate electrode 17 is an insulating film. Fig. 1 Fig. 2 vo (volt) Fig. 40 Fig. 5 Fig. 611i5 VD (volt)
Claims (1)
高分子半導体膜、該高分子半導体膜(;電圧を印加して
空乏層を生成する為のゲート被膜、該ゲート被膜直下C
二生成されたゲート領域を間にした前記高分子半導体膜
上C二形成されたオーミック接触するソース電極及びド
レイン電極を具備したことを特徴とする高分子半導体電
界効果トランジスタ。 (2、特許請求の範囲第1項記載の高分子半導体電界効
果トランジスタ艦=おいて、前記ゲート被膜は、前記高
分子半導体膜とショットキバリア接合を生成する金属電
極であることを特徴とする高分子半導体電界効果トラン
ジスタ。 (3)特許請求の範囲第1項記載の高分子半導体電界効
果トランジスタにおいて、前記ゲート被膜は、前記高分
子半導体膜上(=形成された絶縁膜及び核絶縁膜上C二
形成された金属電極からなることを特徴とする高分子半
導体電界効果トランジスタ。 (4) 特許請求の範囲第3項記載の高分子半導体電
界効果トランジスタC;おいて、前記絶縁膜はプラズマ
重合膜または熱分解気相重合膜から成ることを特徴とす
る高分子半導体電界効果トランジスタ。 (5)絶縁基板上に形成さnた一導電型を有する高分子
半導体膜と該高分子半導体膜に電圧を印加して空乏層を
生成する為のゲート被膜と該ゲート被膜直下(二生成さ
れたゲート領域を8C;シた前記高分子半導体膜上5二
形成されたオーミック接触するソース電極及びドレイン
電極とを備えた高分子半導体電界効果トランジスタを製
造する方法6二おいて、前記絶縁基板上に所定のレジス
トパターンを形成した後該レジストパターン上に高分子
半導体膜を重合ζ二より形成し、次いで鱒状の1七トン
をその表ij口噴霧した後リフトオフ法1;より前記レ
ジストと共1=前記高分子半導体膜の一部を剥離して所
定パターンの前記高分子半導体膜な形成する工程を含ん
でいることを特徴とする高分子半導体電界効果トランジ
スタの製造方法。[Scope of Claims] (1) A polymer semiconductor film having one conductivity type formed on an insulating substrate; a gate coating for generating a depletion layer by applying a voltage; Directly below the gate coating C
A polymer semiconductor field effect transistor comprising a source electrode and a drain electrode that are in ohmic contact with each other and are formed on the polymer semiconductor film with two gate regions interposed therebetween. (2. A polymer semiconductor field effect transistor according to claim 1, wherein the gate film is a metal electrode that forms a Schottky barrier junction with the polymer semiconductor film. Molecular semiconductor field effect transistor. (3) In the polymer semiconductor field effect transistor according to claim 1, the gate film is formed on the polymer semiconductor film (=on the formed insulating film and on the core insulating film). A polymer semiconductor field effect transistor comprising two metal electrodes. (4) A polymer semiconductor field effect transistor C according to claim 3; wherein the insulating film is a plasma polymerized film. or a polymer semiconductor field effect transistor comprising a pyrolytic vapor phase polymerized film. (5) A polymer semiconductor film having one conductivity type formed on an insulating substrate and a voltage applied to the polymer semiconductor film. A gate film for applying voltage to generate a depletion layer, and a source electrode and a drain electrode that make ohmic contact are formed directly under the gate film (the generated gate region is 8C) and on the polymer semiconductor film. In the method 62 for manufacturing a polymer semiconductor field effect transistor, a predetermined resist pattern is formed on the insulating substrate, and then a polymer semiconductor film is formed on the resist pattern by polymerization. Lift-off method 1: After spraying 17 tons of the polymer semiconductor film onto the surface thereof, a part of the polymer semiconductor film is peeled off along with the resist to form a predetermined pattern of the polymer semiconductor film. A method for manufacturing a polymer semiconductor field effect transistor, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56214985A JPS58114465A (en) | 1981-12-26 | 1981-12-26 | High molecular semiconductor field effect transistor and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56214985A JPS58114465A (en) | 1981-12-26 | 1981-12-26 | High molecular semiconductor field effect transistor and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58114465A true JPS58114465A (en) | 1983-07-07 |
Family
ID=16664790
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56214985A Pending JPS58114465A (en) | 1981-12-26 | 1981-12-26 | High molecular semiconductor field effect transistor and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58114465A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6285467A (en) * | 1985-10-09 | 1987-04-18 | Mitsubishi Electric Corp | field effect transistor |
JPS6285224A (en) * | 1985-10-09 | 1987-04-18 | Mitsubishi Electric Corp | Liquid crystal display device |
JPS62183181A (en) * | 1986-02-06 | 1987-08-11 | Matsushita Electric Ind Co Ltd | Field effect transistor and its manufacturing method |
JPS6376378A (en) * | 1986-09-18 | 1988-04-06 | Mitsubishi Electric Corp | field effect transistor |
JPH01193640A (en) * | 1988-01-28 | 1989-08-03 | Matsushita Electric Ind Co Ltd | Fet sensor |
US5017975A (en) * | 1988-07-15 | 1991-05-21 | Matsushita Electric Industrial Co., Ltd. | Organic electronic device with a monomolecular layer or multi-monomolecular layer having electroconductive conjugated bonds |
US5153681A (en) * | 1989-07-25 | 1992-10-06 | Matsushita Electric Industrial Co., Ltd. | Electrcally plastic device and its control method |
US5705826A (en) * | 1994-06-28 | 1998-01-06 | Hitachi, Ltd. | Field-effect transistor having a semiconductor layer made of an organic compound |
US6348700B1 (en) | 1998-10-27 | 2002-02-19 | The Mitre Corporation | Monomolecular rectifying wire and logic based thereupon |
-
1981
- 1981-12-26 JP JP56214985A patent/JPS58114465A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6285467A (en) * | 1985-10-09 | 1987-04-18 | Mitsubishi Electric Corp | field effect transistor |
JPS6285224A (en) * | 1985-10-09 | 1987-04-18 | Mitsubishi Electric Corp | Liquid crystal display device |
JPS62183181A (en) * | 1986-02-06 | 1987-08-11 | Matsushita Electric Ind Co Ltd | Field effect transistor and its manufacturing method |
JPS6376378A (en) * | 1986-09-18 | 1988-04-06 | Mitsubishi Electric Corp | field effect transistor |
JPH01193640A (en) * | 1988-01-28 | 1989-08-03 | Matsushita Electric Ind Co Ltd | Fet sensor |
US5017975A (en) * | 1988-07-15 | 1991-05-21 | Matsushita Electric Industrial Co., Ltd. | Organic electronic device with a monomolecular layer or multi-monomolecular layer having electroconductive conjugated bonds |
US5153681A (en) * | 1989-07-25 | 1992-10-06 | Matsushita Electric Industrial Co., Ltd. | Electrcally plastic device and its control method |
US5705826A (en) * | 1994-06-28 | 1998-01-06 | Hitachi, Ltd. | Field-effect transistor having a semiconductor layer made of an organic compound |
US6348700B1 (en) | 1998-10-27 | 2002-02-19 | The Mitre Corporation | Monomolecular rectifying wire and logic based thereupon |
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