JPS58114387A - Data processing device with buffer memory - Google Patents

Abstract

PURPOSE:To facilitate the process of an error which is generated to another word within a block, by loading the data equivalent to one word to be rewritten in the end within a block in a writing mode and when a block is loaded into a memory. CONSTITUTION:When no desired data exists in a buffer memory 1 in a writing mode, a block equivalent to 4 words for example are loaded through a main storage device 7. Then the presence or absence of an error is checked by a checking circuit 2 for each word, and the result of checking is shifted to a buffer register 4 to be written in the memory 1. In this case, the desired data equivalent to one word to be rewritten is loaded in the end within a block. Thus the loading of data is through. Therefore such a state is never caused that a part of one clock exists in the memory 1 and the rest part existing only on the device 7. Thus it is facilitated to process an error which occurs to one word of the corresponding block.

Description

DETAILED DESCRIPTION OF THE INVENTION (AJ) Technical Field of the Invention The present invention relates to a data processing device having a buffer system,
In particular, in a data processing device having a buffer memory where so-called swap control is performed, when a boot load is performed during IF loading processing, one word of data including the write to be rewritten is Data that has a buffer memory that is designed to be loaded last in the bootstack and to facilitate error handling when an error occurs during loading of at least one other word of the bootstack. It relates to a processing device.

ta) Technical Background and Points of Interest Conventionally, in data processors 31 having a buffer memory, control over the buffer memory can be roughly divided into two methods. One is called the store-through method, and the other is called the swap method.The 1WK method is relatively easy to control, so it can be used in data processing systems of relatively small base machines. This is adopted and a first-order type of control is performed. That is.

1) When the desired data is /

If it does not exist on the main memory! i! From the value, one booter's worth of data including the desired data is stored on the buffer memory at a time, so to speak, is fetched and bypassed, and transferred to the arithmetic unit (the same applies to the store-through type).

ii) During the write process, if the desired data does not exist on the buffer memory, 11272 minutes of data including the desired data are loaded onto the buffer memory from the main memory**. And regarding the above desired data.

Rewriting is performed on the buffer memory, and rewriting is not performed on the main memory (in the case of a store-through type, rewriting is performed on the main memory).

In the case of the swap method, control is performed as described above, but
Conventionally, when loading one block of data f1 words at a time from the main memory IIIi as described above.

The 111th minute, which includes the desired data to be rewritten, is placed in front of other pieces of candy.

I was trying to finish the continuous loading/writing process quickly and move on to the next process. Misaki: When loading other words, I don't necessarily have to execute them immediately.

I was only able to do it as quickly as possible.

However, in the case of write processing, Figure 11 (A) tll (
As will be described later with reference to C), it becomes difficult to correct an error when an error occurs.

(C1 Object and Structure of the Invention The present invention aims to solve the above points.) A data processing device having a buffer memory according to the present invention transmits and retains the contents of the main memory in units of blocks. In addition, if desired data exists on the buffer memory during write processing, the desired data is not written on the buffer memory, and the desired data is written on the buffer memory. If the data does not exist, the controller transmits one booter unit of data including the desired data from the main storage device, and arranges so that the rewritten version of the desired data is located on the buffer memory. In a data processing device having a buffer memory that can be controlled, when the l booter unit of data is transmitted from the main storage device in predetermined units of l:L nits, the effective one of each unit of data is !1: Check circuit section to check f and @
Checked by Cheno 2 circuit section luniy)S)
the data is sequentially loaded into the buffer memory, and when the desired data does not exist on the buffer memory during the write process, the data is loaded from the main memory in units of 1 pk. data of 1
Control is performed so that the desired data is transmitted unit by unit as the last unit, and the desired data is rewritten while other units are normally stored on the buffer T memory. The feature is that the data is controlled to be stored on the buffer memory.

This will be explained below with reference to the drawings.

ID) Embodiment 11 of the invention Figure 11 is an explanatory diagram explaining the conventional and embodiment 11jA* of the present invention regarding successive write control in the swap method.IBI shows the conventional aspect of write control in the swap method. An explanatory diagram for explaining.

FIG. 11 (C1 is an explanation (3) for explaining the configuration of an embodiment of the present invention regarding write control in the swap method, and the second figure shows the configuration of an embodiment of the present invention.

In 21(8), l is a buffer memory, 2 is a check circuit section, 3 is a --do l & tan section, 4 is a buffer register, and 5 is a merging circuit section, which is loaded from the storage device. 1 candy and write data to be rewritten (W
D) is merged, for example, in units of 4 bytes, and 6 represents an l booter which is temporarily loaded on the buffer memory.

For example, the l booter is 32 bytes.

The following explanation assumes that one word is 8 bytes and the unit of marring is 4 bytes. The explanation is based on the assumption that 4 times of μ-doing is performed for each word at the time of one write, and suppose that addresses 1000 to 101F (in hexadecimal notation) are
Of the data on Bootsk.

The following description assumes that addresses 1010 to 1013 are processed.

If the desired data does not exist in the buffer memory l during the bladder evacuation process, the 11
972 minutes of data is transferred. In this case, if data at addresses 1010 to 1013 are to be read as described above, address 1 is read as shown in the figure.
Load data for one word from 010 to 1017 first, 00 then address X101BF! l0IF lI
I minute I) f-11ke-code 00 then address 100
111 minutes of data from 0 to 1007 ft--
Then, the value for loading data for li1 at addresses 1oos to 100F is set. And address 1xo
When data for one word from to to 1017 is transferred from the check circuit section 2 to the buffer register 4,
A write to the buffer memory and the fetch bypass described above is performed.

Figure 21 (Hitoshi shows an explanatory diagram explaining the conventional aspect of write control in the swap method. In the conventional aspect, as in the case shown in O1 (6) and (8), the desired data is 188 minutes of data including address 1010
The data from 1017 to 1017 are first read. When the data is transferred from the check circuit unit 2 to the buffer register 4, it is marred with the write data WD and written to the buffer memo SJl. Also, the data for one candy at addresses 1018 to 101F follows.

727 and is transferred to register 4, and is not marred (written to buffer mesosu l).

In the past, write processing was performed in this way.

It turns out that the following problems occur. 111, when data corresponding to one block is read word by word from the main memory **, the check circuit section 2 checks whether an error has occurred in each word. Now if 7
111 minute day of dresses 1010 to 1017! is merged with the write data in the marginal circuit section 5 as described above and written to the buffer memory, and then the data of other candy are sequentially written to the buffer memory as shown in ■, ■, ■.
0 if an error occurs when trying to write to
For example, if an error occurs in the data for llj at addresses 1018 to 1017, the correct data at that point is 111 at addresses 1010 to 1017.
data on the buffer memory l.

Data for other words exists in the main memory. In the central easy-to-use device, since one word of data at addresses 1010 to 1017 has been written, it is in a state where it is in the 1&process of the 0th order instruction. It has been found that when such a situation occurs, the process for dealing with errors becomes extremely complicated.

Therefore, in the present invention, one word of data containing desired data is j! Load it into kII. That is, 0 shown, ■, ■.

■As in
Make it written to the memo vl. and address 10
The data of Ill from 10 to 1017 is written to the buffer memory νl and the data of Ill of 10 to 1017 is written to the buffer memory νl and the data of Ill of 10 to 1017 is written to the buffer memory νl and the data of 11. When the device starts processing the next command, ensure that the data of other candy in the boot stock is written without error in the buffer memory. .

This greatly simplifies the process for dealing with errors. That is, even if an error occurs in the data of the other words, it is guaranteed that the correct data exists on the main memory.

As a countermeasure for errors, it is sufficient to load the file again.

2i11 shows the configuration of an embodiment of the present invention, where the symbols 1 through 5 correspond to 21 factors, 7 is a main memory, 8 is a central processing unit, and 9 is a read register.

lO represents the off-circle.

When the desired data does not exist on the buffer memory l during read processing or write processing.

As mentioned above, the data for l pulls is loaded from the main memory 5liIll17, for example 4m, and the check circuit unit 2 checks whether there is an error for each word.
Then, the buffer is shifted to register 4, and the buffer is written to register 4.

During the read process, the im containing the desired data is
When the data for 1 is set in the register 4, it is fetched and bypassed via the off circuit IO. Further, during the write process, when one word of data including the desired data I is shifted to the register 4, the merging circuit 5 outputs the write data! Merged with WD. Then, the merged data for one word is written to the buffer memory l. Note that the read register 9 is used when desired data is successively output from the buffer register 1.

According to the present invention, when one word of data containing the desired data has been loaded into the buffer memory, other words constituting the boot The buffer has been completed and the memory has been opened without any error. Therefore, the state as explained with reference to Fig. 1 (5), that is, °1.
This eliminates a situation where some items exist only on the memory and other items only on the main storage, and error handling becomes easier.

[Brief explanation of the drawing]

Figure 1 shows an explanation (3) explaining the conventional and one embodiment of the present invention regarding successive output control in the swap method;
Figure 1 (Bl is an explanatory diagram explaining a conventional aspect of write control in the swap method, *Figure 1 (q is an explanatory factor explaining an embodiment of the present invention regarding write control in the swap method, the second factor is The configuration of an embodiment of the present invention is shown.In E, l is a buffer memory, 2 is a check circuit section, and 3
4 is a variable register, 5 is a merging circuit, 7 is a main memory, and 8 is a central processing unit. Patent applicant Fujitsu Limited

Claims (1)

[Scope of Claims] The present invention includes a buffer memory for transmitting and retaining contents on a main memory device in units of tl booters. If the desired data exists on the buffer memory at the time of write processing, the desired data is written on the buffer memory, and when the desired data does not exist on the buffer memory, the desired data is written. A data processing device having a buffer memory that is controlled so that data in units of 1 block including data of 1 μm is transmitted from the main storage device and the rewritten state of the desired data is located on the buffer memory. In the device. A check circuit section that checks the validity of the data for one unit of incense sticks when the data for one unit of incense is transmitted from the main storage device for each predetermined unit of 71 minutes, and the check circuit and a p-do processing section that sequentially loads 71 worth of data checked by the unit into the buffer γ memory, and when the desired data does not exist on the buffer memory during the write process, Control is performed so that the desired data is transmitted one block at a time from the main memory am as the last unit, and other units are normally stored on the buffer memory iJ. A data processing device having a buffer memory, characterized in that the desired data is controlled to be stored in the buffer memory in a rewritten state depending on the state.