JPS58112373A - Manufacture of gaas ic - Google Patents

Abstract

PURPOSE:To obtain a planar structural GaAs IC which can improve the reliability of wiring, by etching an insulation film used as a spacer resulting in the flat formation of the substrate surface after electrode formation. CONSTITUTION:On the semi-insulating GaAs substrate 21, an SiO2 film 231 is deposited by a low temperature CVD method, or an Si3N4 film 232 is deposited by a plasma CVD method. Next, with a photo resist film 24 as a mask, the Si3N4, and SiO2 of the source and drain regions are succeedingly etched and opened window, thereafter AuGe films 251-253 are formed, the lift-off method to remove the resist film 24 is performed, and they are alloy-treated resulting in the formation of ohmic electrodes 251 and 253. Thereafter, only the Si3N4 film 232 is removed by a plasma etching, succeedingly the SiO2 film 231 is opened window for a gate electrode by a photoetching, and thus a Schottky electrode 26 constituted of a Pt film is formed by a lift-off process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing an integrated circuit using gallium arsenide (hereinafter referred to as GaAs), and particularly to an improvement in the process of forming electrodes and wiring.

[Technical background of the invention]

GaA1 integrated circuits are faster and faster than conventional St integrated circuits.
It has the characteristic of operating with low power consumption, and has been the subject of much research and development.

This GaA@ integrated circuit is, for example, a Schottky barrier gate field effect transistor (ME8 FE) using a PT gate.
T) Manufactured as one basic element. An example of the manufacturing process will be explained using FIG. 1.

That is, 81 ions were selectively implanted only into the formation region of a conductive layer such as an FET on a semi-insulating GaAs substrate, and the temperature was increased to 800°C.
After annealing at the above temperature to form active @12, S10
．． Depositing film 13 (a).

Next, using the photoresist film 14 as an electrode mask, StO
The film is chemically etched (e), and a metal film 15 (1g1 to tss) for electrodes made of aluminum 11G, alloy, gold, etc. is deposited (e).
. Then, the resist film 14 is removed, the vapor-deposited metal film 15.1 in areas other than the ohmic electrode formation area is removed, and the metal film 15.1 is alloyed at a temperature of 400°C or higher to form the source and drain ohmic electrodes I.
form s,,Is,(d). Thereafter, using the same lift-off method as above, a Schottky electrode 16 that will become a gate electrode is formed using, for example, PT, and furthermore, a wiring "5e17* is formed directly on this (via an interlayer insulating film). (・).

[Problems with background technology]

In the conventional device manufacturing process, the active layer 12 is formed by a precisely controlled ion implantation method, and is a simple manufacturing process in which the GaAs surface is not processed at all and has a planar structure. The feature lies in the frequent use of a lift-off process using the insulating film 13 as a spacer.For example, the source-drain electrode phase ohmic electrode I5.

In No. 15, it is customary to use an Au-based alloy in GaAs crystals, and it is difficult to etch only the metal without damaging the GaAs crystals, so the lift-off method is unavoidable for patterning.

By the way, in order to complete this lift-off process, the insulating film that serves as a spacer must be sufficiently thicker than the metal film, but the difference in level between the metal film and the insulating film can cause disconnection during the next wiring process. Become. Wire breakage due to this step has a significant impact on yield in the manufacture of integrated circuits. In nine devices using GaAs crystal, which is an expensive material, improving yield is an important issue along with improving performance.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks of the prior art and provides a method for manufacturing a GaAs integrated circuit having a nine-planar structure, making it possible to improve the reliability of wiring.

[Summary of the invention]

In the present invention, when two or more types of electrodes are formed using an insulating film as a spacer in at least two lift-off processes, a 1 m process is required to planarize the substrate surface after electrode formation by etching the insulating film used as a spacer. establish. Specifically, for example, if two or more types of electrode films have different thicknesses, the insulating film that will serve as a spacer may be removed in advance by removing a stack of insulating films with different etching characteristics and used as a spacer in the next electrode film lift-off process. . Also, KL''C may be used to eliminate the step difference by etching the insulating film used as a spacer after completing all the multiple lift-off steps.

〔Effect of the invention〕

According to the present invention, when a lift-off process is used to form electrodes of a GaAs integrated circuit with a planar structure such as a MEBFET, the surface is flattened to prevent broken lines in wiring, thereby improving the reliability of the GaAs integrated circuit.

Yield can be improved.

[Embodiments of the invention]

FIGS. 2(1) to 2) show the manufacturing process of a planar structure MIC8FET in one embodiment of the present invention.

First, selective ion implantation and annealing are performed to form the active layer 2.
Low-temperature CV on the semi-insulating GaA1 substrate 2 formed in 21
90.1 pm of 810° Mxatt was deposited by D method,
Next, the plasma CvD method has a diameter of 10.2 μm. N, film 22 S is deposited (1).

Next, using the photoresist film 24 as a mask, the source and drain regions are Si, N, 810. Sequentially etching to open the window b), then 0.25 μm AuGe
Film 25 (25, ~25.) 'fr is formed (e)
. Then, a lift-off method is performed to remove the resist film 24t, and alloy processing is performed to form the ohmic electrodes 25, , 25.
t-form (d). After this, 81. N4 membrane 23. Remove only (・). Subsequently, photoetching was performed with 0.1 pm of 810.
Membrane 23. A window is made for the gate electrode, and a Schottky electrode 26 made of a PT film, which is a gate electrode, is formed by the same lift-off method (f).

After sintering, deposit an interlayer insulating film 17, form through holes, and connect! '1 t '' l).

According to this embodiment, 810. Membrane 23. and ohmic electrode,? 51...? ! , and the key electrode 26, the interlayer insulating film 27 is coated very smoothly. As a result, the second layer L*za, 2g,
There were no wire breaks, and reliability was significantly improved. In other words, by stacking and using two types of films with different etching characteristics as an insulating film used as a spacer when performing multiple lift-offs, two types of electrodes with different film thicknesses are formed, and the reliability is improved by %. This makes it possible to create two-layer wiring with high performance.

In the above embodiment, 810. , ss, a, was deposited on the application, but on the other hand, o, xpm's 811 N4, 0.2
GM's 840. JIK deposition may also be performed. In this case, 810. after forming the ohmic electrode. When removing the
Normal S* etching with HF can be performed, but dry etching is of course also possible.

Also, the insulating film is 810. ．． 81. The combination is not limited to N4. Incidentally, in the embodiment, a method for manufacturing a GaAa MESFET is described.

This method can also be applied to other GaAm planar devices in which two or more types of electrodes or interconnections with different film thicknesses are formed.

Furthermore, by increasing the number of laminated insulating films, it is possible to apply the present invention to electrodes or wiring having three or more types of film thicknesses different from each other.

FIGS. 3(a) to 3(g) are diagrams for explaining another embodiment of the present invention. First, an active layer 32 is formed on a semi-insulating GaAm substrate 31 by selective ion implantation and annealing. After the formation, a film 33 of 3000A is deposited by the CVD method (a). Next, windows are opened in the source and drain regions by photolithography using the photoresist film 34 (
b). And about 1
00OA evaporated e), mu on photoresist 34
Gmg35B is removed together with the photoresist film 34 by lift-off, and alloyed in an H2 atmosphere to form a source.

Drain ohmic electrode 35. ．． Form 35□ (d).

Subsequently, a gate electrode is formed using a similar lift-off method. That is, first, a window is opened in the gate area using photo-etching technology, and S+02g33@ of the gate area is formed.
It is removed by reactive ion etching to form a Schottky electrode 36 made of an At film (e). In this state 5i0
The difference in film thickness between the two films 33, the ohmic electrode 351.35□ and the Schottky electrode 36 is 2000A, but R
Etch the 5i02 film 33 using IE, and stop etching when the difference in film thickness has almost disappeared.
(f). Next, using TL Pt Au, wire 3
7. ．． 3? (g).

Gate width 25μm and gate length 1 created in the above process
When we prepared 20 transistor arrays in which 100 p m MES FETs were arranged and operated them, RIE
It was found that the yield was significantly higher than when no planarization process was performed to eliminate surface differences.

In this example, the film thickness of the SIO and the film thickness of each electrode were measured.
The difference is etched by controlling the RIB, but as a method for controlling the amount of etching, a method may be adopted in which a type 211 film using a different etching method is deposited as an insulating film.

[Brief explanation of drawings]

Figure 1 (a) - (s)! ri Conventional 01 person m -M
Round diagrams illustrating the manufacturing process of H8FET, FIGS. 2(a) to 2) are GaAs-M
] Diagrams for explaining the manufacturing process of C8FET, 3rd figure) to (g) are GaAs-ME8FE in other examples
It is a figure for explaining the manufacturing process of T. 21.31...Semi-insulating QaAs substrate, 22°32.
...Active layer, 123. ...810. membrane, 23. ...
St, N, l [, 33...810. film,! 4.34・
...Photoresist film, 25. ~is,,ss,~As
@””kuG@membrane, 25. ,! ! ,,35. . 35... Ohmic electrode, 26.36... Seat key electrode, 27... Interlayer insulating film. 711.2B, 37. ．． 371...Wiring. Applicant's agent Patent attorney Takehiko Suzue 1! 2 Figure Shin 2 Figure 3 Matter 3 Figure

Claims (1)

[Claims] (1) A step of forming two or more types of electrodes on a GaA substrate by at least 42 lift-off steps using an insulating film as a spacer, and etching the insulating film used as the spacer. A method for manufacturing a GaAs integrated circuit, comprising the steps of flattening the substrate surface mt after electrode formation, and forming wiring connecting between each element. In the step of flattening the surface of the substrate, films having different etching properties are sequentially removed from above as insulating films to be spacers to be used as the next spacer. A method of manufacturing a GaAs integrated circuit. (3) Step 1 of flattening the substrate surface is to use it as a spacer and remove the step by etching after several times of electrode lift oxidation. A method of manufacturing the GaAs integrated enclosure described.