JPS58110046A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58110046A JPS58110046A JP20878581A JP20878581A JPS58110046A JP S58110046 A JPS58110046 A JP S58110046A JP 20878581 A JP20878581 A JP 20878581A JP 20878581 A JP20878581 A JP 20878581A JP S58110046 A JPS58110046 A JP S58110046A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- substrate
- film
- film thickness
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明り半導体装置の製造方法、特に半導体基板上に金
属パターンを形成する工程を含む半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a step of forming a metal pattern on a semiconductor substrate.
従来、半導体基板上に金属パターンを形成する方法とし
ては、基板上に金属膜を形成した後、ホトレジストによ
りパターンの形成を行い、ホトレジストをマスクとして
金属膜をエツチングして部分的に除去する方法と、基板
上に、先ず、ホトレジストによるパターンを形成し、た
り、金ｐＡ膜の形成を行ない、リフトオフを行なう方法
が知られている。しかし、両方法とも、安定したパター
ンが ′得られる寸法が、レジストの持つ解像虹力に
よって決まシ、後者では、金、Ｅ膜の形成時にＸ；板上
にホトレジストが存在するため、金【と基板間に不純物
が残）やすいといりた欠点があった。Conventionally, methods for forming metal patterns on semiconductor substrates include forming a metal film on the substrate, forming a pattern using photoresist, and partially removing the metal film by etching using the photoresist as a mask. A known method is to first form a photoresist pattern on a substrate, or to form a gold pA film, and then perform lift-off. However, in both methods, the dimensions at which a stable pattern can be obtained are determined by the resolving power of the resist. It has the disadvantage that impurities tend to remain in between.
本発明の目的は、従来のホトレジスト使用による欠点を
なくして、微細でかつ安定な金属パターンを、半導体基
板上に容易に形、成することを可能にした半導体装置の
製造方法を拶伊するにるる。The purpose of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the disadvantages of using conventional photoresists and makes it possible to easily form fine and stable metal patterns on a semiconductor substrate. Ruru.
本発明の皺造方法は、半導体ｆ−析板上急峻な傾斜の段
差を形成し、つぎに、前記段差のある基板全面に、蒸着
またはスパッタ重ｉ飯による斜於方向から放射される金
属粒子により前記段差を含む基板全面に金属膜を形成し
、つぎに平行平板型プラズマエツチングなどの方向性エ
ツチングによシ前記基板に対し垂直方向のエツチングを
行い前記段差部側面に金属パターンを残す工程を含んで
いる。The wrinkle forming method of the present invention is to form a step with a steep slope on a semiconductor f-deposition plate, and then to emit metal particles from an oblique direction by vapor deposition or sputtering over the entire surface of the substrate with the step. forming a metal film on the entire surface of the substrate including the step, and then etching in a direction perpendicular to the substrate by directional etching such as parallel plate plasma etching to leave a metal pattern on the side surface of the step. Contains.
本発明方法では、金属膜の形成から金属パターンを得る
までの間ホトレジストを使用せず、かつ形成てれる金属
パターンの寸法は、初めに被着する金属膜の膜厚および
、金属膜形成時の金属粒子放射方向によシ制御されるの
で、従来のホトレジストの場合のようにホトレジストの
解像力に制限されない、微細でかつ安定な金属パターン
を得ることができる。In the method of the present invention, no photoresist is used between the formation of the metal film and the formation of the metal pattern, and the dimensions of the formed metal pattern are determined by the thickness of the initially deposited metal film and the time at which the metal film is formed. Since the radiation direction of the metal particles is controlled, it is possible to obtain a fine and stable metal pattern that is not limited by the resolution of the photoresist as in the case of conventional photoresists.
つぎに本発明を実施例によシ説明する。Next, the present invention will be explained using examples.
第１図ないし第６図は本発明の一実施例の創造工程順の
断面図である。まず、第１図に示すように、酸化シリコ
ン２を形成した半導体基板ｌ上に、ホトレジストによシ
バターンを形成し、酸化シリコン２をエツチングした後
、ホトレジストの除去を行い、第２図のような、基板１
上に段差２ａを得る。FIGS. 1 to 6 are cross-sectional views illustrating the order of the creation process according to an embodiment of the present invention. First, as shown in FIG. 1, a pattern is formed using photoresist on a semiconductor substrate l on which silicon oxide 2 is formed, and after etching the silicon oxide 2, the photoresist is removed, and as shown in FIG. , substrate 1
A step 2a is obtained at the top.
次に、第３図矢印５で示される通シ、蒸着装置を九杜ス
パッタ装置により、基板斜め上方向よシ金属粒子が飛来
する形で、第４図に示すように、金属膜４Ｑ形成を行な
う。これよシ、段差部２８側１［ｆＫついても金属ＩＭ
４が形成される。ここで、段差部２ｇ側面の金属膜の膜
厚を基板垂直方向にみると、゛基板水平部に形成された
金ｓｍｍに、段差量を加えた値になる。つぎに、平行平
板型プラズマエツチング装置によシ、第５図矢印６で示
される通シ、基板に対してに直方向にエツチングが進行
するよう基板全面にエツチングを行なう。この際、エツ
チングされる金！Ｉ４膜厚を基板水平部金属膜厚と段差
側面の金属膜厚の中間に選ぶ事にょシ、段差部側面の金
属膜は、第６図に示すとおシエッチングで除去されず残
るｉになる。以上の処１１によシ、金属パターンを基板
上に形成する事ができる。Next, as shown in FIG. 4, a metal film 4Q is formed by using a Kuto sputtering device to pass through the evaporation device as shown by arrow 5 in FIG. Let's do it. This is it, step part 28 side 1 [fK is metal IM
4 is formed. Here, when looking at the thickness of the metal film on the side surface of the stepped portion 2g in the vertical direction of the substrate, it becomes the sum of the amount of the stepped portion and the gold smm formed on the horizontal portion of the substrate. Next, the entire surface of the substrate is etched using a parallel plate type plasma etching apparatus so that the etching progresses perpendicularly to the substrate in the direction indicated by the arrow 6 in FIG. At this time, the money being etched! If the thickness of the I4 film is selected to be between the thickness of the metal film on the horizontal part of the substrate and the thickness of the metal film on the side surfaces of the step, the metal film on the side surfaces of the step will remain i without being removed by etching, as shown in FIG. According to step 11 above, a metal pattern can be formed on the substrate.
第７図線、本発明の他の実施例における工程途中の一断
面図である。第７図の例では、前記＃ｇ１図の段階から
、酸化シリコン２の上にホトレジスト膜３を形成し、ホ
トエツチングにょシ段差３ａを形成し九状態を示してい
る。この段差３ａに対し、前記第３図以下の説明と同様
にして、段差部 １３ａの側面に金属パターンを残す
の゛である。FIG. 7 is a cross-sectional view in the middle of a process in another embodiment of the present invention. In the example of FIG. 7, a photoresist film 3 is formed on the silicon oxide 2 from the stage shown in FIG. #g1, and a step 3a is formed by photoetching. With respect to this step 3a, a metal pattern is left on the side surface of the step 13a in the same manner as described in FIGS. 3 and below.
以上炒明しン処理によシ形成した金属パターンの寸法は
、その幅においては段差部に水平方向に形成された金属
膜厚と同一でＬＪ）、高さは、段差量からオーバーエツ
チング分を除いえ値になる。The dimensions of the metal pattern formed by the above-mentioned etching process are the width (LJ), which is the same as the thickness of the metal film formed horizontally on the step part (LJ), and the height, which is calculated by subtracting the amount of overetching from the amount of the step. It will be a negative value.
ここて段差部水平方向の金属膜厚は、基板水平部の膜厚
と比例し、かつ形成金属の入射方向と相関があることが
明らかであシ、基板上に形成する段差量、形成する金属
の膜厚及びその入射表向を制御する事により、基板上に
安定に微細な金属パターンを形成することができる。It is clear that the metal film thickness in the horizontal direction of the step part is proportional to the film thickness in the horizontal part of the substrate and has a correlation with the direction of incidence of the forming metal. By controlling the film thickness and its incident surface direction, a fine metal pattern can be stably formed on the substrate.
また、基板に対する形成金属の入射角度を一定にし、多
方向よシミ属膜の形成を行うことにょシ、１本のレジス
トパターンに対して２本の段差が発生することを利用し
２本の金属パターンを得ることができる。In addition, in order to form a stain film in multiple directions by keeping the angle of incidence of the forming metal on the substrate constant, it is possible to make use of the fact that two steps occur for one resist pattern. You can get the pattern.
表お、本発明は、半導体装置全搬に適用可能であるが、
特にＧａＡｓＦＥＴに対して有効である。Although the present invention is applicable to all transportation of semiconductor devices,
This is particularly effective for GaAsFETs.
第１図ないし第６図は、本発明の一実施例を説明すゐた
めの断面図、鮪７図は本発明の他の実施例Ｏ１ｌ造工程
途中の一段階における断面図である。
１−−−−・・半導体基板、２・・・・・・酸化シリコ
ン、２ｇ・・・・・・酸化シリコンの段差、３・・・・
・・ホトレジスト族、３ａ・・・・・・ホトレジスト膜
の段差、４・・・・・・金属膜、５・・・・・・金属粒
子放射方向、６・・・・・・エツチング方向。
第を図
第２図
第３図
第４図
第５ 図
第６図
第７図1 to 6 are cross-sectional views for explaining one embodiment of the present invention, and Figure 7 is a cross-sectional view at one stage during the production process of another embodiment of the present invention. 1----...Semiconductor substrate, 2...Silicon oxide, 2g...Silicon oxide step, 3...
... Photoresist group, 3a ... Step difference in photoresist film, 4 ... Metal film, 5 ... Metal particle radiation direction, 6 ... Etching direction. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7
Claims (1)
記段差のある基板全面に、蒸着装置ｔｔたはスパッタ装
置による斜め方向から放射される金属粒子によシ前記段
差部を含む基板全面に金属膜を形成し、つぎに平行平板
型プラズマエツチングなどの方向性エツチングによシ前
記基板に対し垂直方向のエツチングを行い前記段差部側
面に金属パターンを残す工程を含むことを特徴とする半
導体装置の製造方法。A steeply inclined step is formed on a semiconductor substrate, and then metal particles emitted from an oblique direction by a vapor deposition device TT or a sputtering device are applied to the entire surface of the substrate including the step portion. A semiconductor characterized by comprising the steps of forming a metal film on the substrate, and then etching the substrate in a direction perpendicular to the substrate by directional etching such as parallel plate plasma etching to leave a metal pattern on the side surface of the stepped portion. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20878581A JPS58110046A (en) | 1981-12-23 | 1981-12-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20878581A JPS58110046A (en) | 1981-12-23 | 1981-12-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58110046A true JPS58110046A (en) | 1983-06-30 |
Family
ID=16562059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20878581A Pending JPS58110046A (en) | 1981-12-23 | 1981-12-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58110046A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0179196A2 (en) * | 1984-06-22 | 1986-04-30 | International Business Machines Corporation | A method of forming a semiconductor device using a mask |
-
1981
- 1981-12-23 JP JP20878581A patent/JPS58110046A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0179196A2 (en) * | 1984-06-22 | 1986-04-30 | International Business Machines Corporation | A method of forming a semiconductor device using a mask |
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