JPS58108090A - Memory circuit - Google Patents

Abstract

PURPOSE:To reduce the offset voltage of a sense amplifying circuit in distribution width effectively by providing a correcting memory cell and corecting the sense amplification output of a main memory. CONSTITUTION:The output of a main memory selected out of main memories MC1-MCN is detected and amplified by a sense amplifying circuit SA. By this detection output, corresponding corrected values are read out of auxiliary memories M1 and M2 through signal generating circuits G1 and G2 of correcting circuits CL1 and CL2 to correct the output of the amplifying circuit SA. Therefore, the offset voltage distribution width of the sense amplifying circuit is reduced effectively. As a result, a signal voltage outputted from a memory cell to a bit line is reduced and the memory cell is sized small to facilitate the integration of a memory circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density memory circuit that stores information in each memory cell formed in large numbers on a single substrate.

Conventionally, this type of memory circuit has a large number of circuit groups (hereinafter referred to as row circuits) whose configuration is shown in FIG. 1, and a mechanism for selecting memory cells included in each row circuit.
It is provided with a mechanism for inputting and outputting data of a selected memory cell to and from the outside, and a mechanism for controlling the row circuit and the mechanism. As shown in FIG. 1, there are N row circuits (N is an even number of 1 or more).

) memory cells MC,, MC2,...MCfl
MCg, , MCH, 2 pre-charge circuits pc
,, pc2, a sense amplifier circuit SA, a data input/output circuit DIO, 12 bit lines BL,, BL2. It is composed of two dummy cell circuits DC,, DC2, a precharge circuit PC2, a dummy cell circuit DC1, and a 'l Mori cell. MC,, MC2,..., MCJl is connected to the hint line BL1, precharge circuit PC2, dummy cell circuit DC2, memory 4k MC9+1. MC! +2.
--, MCH, data output circuit DIO is bit line B
The sense amplifier circuit SA is connected to the bit lines BL1.L2, respectively. Connected to both BL2. As shown in FIG. 2, the memory cells MC, MC2, . . .
The drain of M is connected to the tip line B, the source of the field effect transistor QM is connected to the first terminal of the capacitor CM, and the second terminal of the capacitor CM is supplied with a DC voltage vDD. The gate of the field effect transistor QM is connected to the word line. Hereinafter, the connection point between the source of the field effect transistor QM and the first terminal of the capacitor CM will be referred to as a node NM. Dummy cell DC1
, DC2 is a field effect transistor Q as shown in FIG.
D.

Consists of QD2 and capacitor CD, QD
The drain of I is connected to bit-, the source of field effect transistor QDI, and the source of field effect transistor QD.
The drains of field effect transistors Q and 1 and the first terminal of capacitor CD are connected to each other, and the gates of field effect transistors Q and 1 are connected to dummy word line DW. connected, capacitor C
A DC voltage vDD is supplied to the second terminal of 9,
A DC voltage v8 is applied to the source of the field effect transistor QD2.
8 is supplied, and a clock signal φB is supplied to the gate of the transistor QD2. Below, the source of the field effect transistor QDI, the field effect transistor QD2
The connection point between the drain of the capacitor CD and the first terminal of the capacitor CD is called a node ND. As shown in FIG. 4, the sense amplifier circuit SA is composed of field effect transistors Q81 and Q8□, and the drain of the field effect transistor Q81 and Q
The gate of field effect transistor Q8□ is connected to bit line BL1, the drain of field effect transistor Q8□ and the gate of field effect transistor QSI are connected to bit line BL2, and the source of field effect transistor Q81 and field effect transistor Q8□ are connected to bit line BL2. The source of is the clock signal φ. is supplied.

In explaining the operation of this conventional memory circuit below, the DC voltage vss is assumed to be a "reference voltage ε," and
DD is assumed to be a high voltage, and a field effect transistor QM.
QDI" QD21 qst* Q8□ are all N-channel type normally-off field effect transistors. In this memory circuit, one bit of memory information is stored in each memory cell, and the memory information is stored in each memory cell. The high and low voltages of the node NM are associated with each other.In order to read the memory zero information from the memory cell, K selects one of the memory cells included in the row circuit, and selects one of the memory cells included in the row circuit. The signal transmitted to the bit line by the memory cell is amplified by the sense amplifier 8A, and the signal is outputted to the outside of the memory circuit through the data input/output circuit DIO. When the memory cell to be selected is connected to the bit line BL1, the dummy cell circuit DC2 is selected (selection of the tummy cell is performed by setting the dummy word line connected to the dummy cell to a high potential). dummy cell circuit DC if the selected memory cell is connected to or disconnected from the bit line BL2.

is selected. In the following explanation, the value of the parasitic capacitance of the bit line BL1 is set as CB, the value of the parasitic capacitance of the bit line BL2 is set as CB□, and the value of the capacitance of the capacitor CM is set as C9.
Let M be the capacitance of the capacitor C9, and C6 be the value of the capacitance of the capacitor C9. A detailed explanation of the operation when memory cell MCN is selected will be given below. Before the read operation is performed, the bit lines BL1, BL1,
BL2 is set to high voltage vDD, and dummy cell circuit D
The connection point ND of the dummy cell circuits DC, DC2 is set to the vss voltage, that is, the reference voltage, by setting the clock signal φ8 supplied to C1 and DC2 to a high potential and then to a low potential again. At this time, the clock signal φ is supplied to the sense amplifier 8A. is set to a high voltage, and field effect transistor Qg1 + 982 is in a non-conducting state. Next, memory cell MC# and dummy cell circuit DC
When 1 is selected, the transistor QM of the memory cell MCN
and the field effect transistor QDI of the dummy cell circuit DC1.
Both become conductive. Since the node ND of the dummy cell circuit DC0 was set to the reference voltage (OV), when the field effect transistor QDI becomes conductive, the bit line B
The charge of L is redistributed between the capacitor CD of the dummy cell circuit DC and the parasitic capacitance of the bit line BL, and the voltage of the bit line BL1 changes from vDD to Co++Cca·vDD. If node NM of memory cell MCN is at voltage ■D
If it is D, even if memory cell MCN is selected, bit line B
The voltage of L2 remains at vDDK. Conversely, if node NM of memory cell McN is 0 [v], when memory cell MCN is selected and field effect transistor QM of memory cell McN becomes conductive, bit i! jB
The voltage of L2 changes from vDD by -6□1.2·Voo K. Usually, the COD design is performed so that the bit line parasitic capacitances CBI and CB2 are equal. In order to reduce the area of the memory cell and realize a high-density storage circuit, the capacitance value C6M of the capacitor CM cannot be increased, and the capacitance value C6M, CoD is reduced by the parasitic capacitance CB1. Compared to CB□, the emergency CB2 CBI is small at “0 c, , , + CCM ” ”” C
RI + cco ""D is a voltage very close to 7..., and the voltage difference is usually less than a few hundred mV. The sense amplifier SA amplifies this minute potential difference between the bit lines BL, BL2.

As described above, after a slight potential difference is applied to the bit lines BL, BL2 by the memory cell and the dummy cell, the clock signal φ is applied. is set to a low potential, and the human lines BL1 and BL2
The charge is discharged through one of the field effect transistors Q8 and Q8□ so that the lower voltage among them becomes an increasingly low voltage, and the bit line BLII BL2
The minute potential difference increases and becomes a large amplitude signal. One memory cell MCN is selected, and the node NM of the memory cell MCN stores a high voltage at cB.

In this case, the bit line BL is connected to □・vDD, and the bit,
cat+cc.

Line BL2 is set to vDD so sense amplifier SAK
Therefore, the bit line BL is set to 0(V)K, and the bit line BL2 is kept at vDD. Since the memory cell McN is selected and the node NM of the memory cell MC has a low voltage, the bit line BL1 is set to CBI°vD by the sense amplifier SA.
D Noma maniho sauce, Hira) 111 BL2 HaO (V
:) CBI + Cc.

is set to In this way, the contents of the selected memory cell are extracted as a large amplitude signal on the bit line,
It is output through the data input/output circuit DIO.

As explained above, the small signal transmitted from the memory cell to the bit line is amplified by the sense amplifier SA into a large amplitude signal, but the threshold voltage of the field effect transistor Qs+-Q82 that constitutes the sense amplifier 8A is are the same, the gain constants of the field effect transistors Q81'Q8□ are the same, and the bit lines BL1. Parasitic capacitance CBI of BL2,
If CB2 is the same, in principle, even the smallest signal can be amplified correctly. However, it is usually difficult to make the above circuit constants exactly the same, and some discrepancies occur. Therefore, the amplitude of the minute signal transmitted to the bit line must be within a certain limit, and for that purpose, the CoM must be larger than a certain limit, which limits the increase in density of this type of memory circuit. This is a big factor.

The present invention is characterized by the addition of a sense amplifier circuit and a mechanism for correcting bit line asymmetry in order to eliminate the drawbacks of the conventional memo circuit.Examples will be described in detail below. To.

As shown in FIG. 5, the row circuit of the memory circuit according to the first embodiment of the present invention is similar to the BL of the conventional memory circuit shown in FIG.
A correction circuit CL is connected to , and a correction circuit CL is connected to BL2.
The structure of the fist is exactly the same as that in Fig. 1, except that 2 is connected. Correction circuit CL, '(Cl3) is signal generation circuit G
1 (G2) and correction memory cells M, (M2), and the signal generation circuits G, (G2) are controlled by the correction memory cells M, (M2).

In the following explanation, similar to the explanation of the operation of the conventional memory circuit above, the DC voltage ■ss is a reference voltage and is assumed to be 0 port, whereas vDD is assumed to be a high voltage, and field effect transistors are not particularly described. As far as possible, it is assumed that it is an N-channel type and a normally-off type. The operation period of the memory circuit of this embodiment is divided into a correction period, a read period, a write period, and a standby period. Of these, the read period is a period during which information that has already been stored is not output to the outside, and as described for conventional memory circuits, minute electrical signals output from memory cells to bit lines are detected. . The operation in the write period is the same as the operation in the read period except that an electric signal larger than the electric signal output from the memory cell is applied from the data input/output circuit DIO to the focus line BL2 of the selected row circuit. be. During the standby period, the word line and dummy word line are set to a low potential, and the bit line is set to a high voltage V. is set to D,
The information stored in each memory cell is held while preparing for the next reading period or writing period. Although the read period, write period, and standby period are provided in conventional memory circuits, the correction period is unique to the present invention and is provided immediately after power-on and prior to the write period and the read period. During the correction period, the asymmetry between the sense amplifier circuit and the bit line of each row circuit is tested, and the test results are stored in the correction memory cells M and M2. In the read period and the write period, prior to the operation of the sense amplifier circuit, the signal generation circuits G1 and G2 generate the hint line B according to the memory contents of the correction memory cells M and M2, respectively.
It operates to adjust the voltages of L and BL2 and cancel out the asymmetry between the sense amplifier circuit and the hit line. If there is asymmetry in the sense amplifier circuit or bit line, bit line BL1
When the voltage of the bit line BL2 is higher than the voltage of the bit line BL2 by a certain voltage or more, the bit line BL is detected as a high voltage, and in other cases, the bit line BL2 is detected as a high voltage. The above-mentioned constant voltage will be referred to as the offset voltage of this sense amplifier circuit. If the offset voltage is positive, the bit line BL1 tends to be detected as a low voltage, and if the offset voltage is negative,
BL has a tendency to be easily detected at high voltage. The offset voltage is a value that fluctuates due to uncertain factors during manufacturing, and also varies depending on each row circuit. Also, the information stored in the correction memory cells M and (M2)K is “
0”, the signal generation circuit G, (G2) is the bit line BL.
Does not affect the voltage of I(BL2). The operation during the correction period will be explained next.

First, information "0" is stored in the correction memory cells M1 and M2, and then, by the same operation as in the write period, the node NM of the memory cells MC and MCN of each row circuit is set to 0 volts. . Next, bit lines BL1 and BL2 are set to high voltage vDD, and dummy cell circuit oc1r DC2
The node ND of is set to 0 port by the clock signal φRK. Next, they will be referred to as memory cells MC1 and DAv8. (V is assumed to be positive.) After setting bit IIIBL to a voltage lower than bit line BL2 by signal amount v8 as described above, sense amplifier circuit SA is operated. If the offset voltage is a value smaller than -v8, the bit line BL is detected as a high voltage and the human line BL2 is detected as a low voltage, and if the offset voltage is a value larger than -v8, the bit line BL is detected as a low voltage. The bit line BL2 is detected as a high voltage. Next, information is input to the correction memory cell M1 according to the large amplitude signal given to the bit line BL by the above operation, and if the bit line BL is at a high voltage, that is, the offset voltage is less than 18 In other cases, information "l" is stored in the correction memory cell M1, and in other cases, information rOJ is stored in the correction memory cell M1. Next, in the same way as above, select the memory cell MCN and the dummy cell DC, and change the bit line BL2 to the bit line BL.
After setting the voltage to be lower by v8 than that of the sense amplifier circuit S
A is operated, and as a result, the large voltage obtained on bit line BL2 is
Information is stored in the correction memory cell M2 according to the amplitude signal. In this way, at the end of the correction period, if the offset voltage is less than -v8, the correction memory cell M
, information "l" is stored in the correction memory cell M2, and information "0" is stored in the correction memory cell M2.
are stored respectively, and when the offset voltage is larger than vs, information rOJ is stored in the correction memory cell M1 and information "1" is stored in the correction memory cell M2. When information "1" is stored in the correction memory cell M1 (M2), the signal generation circuits G, (G2), , adjust the voltage of the bit lines BL, (BL2) before the sense amplifier circuit SA operates. The signal generation circuit G1 (G2) is designed to lower the voltage by 2V8. Therefore, in the read period and write period, if the offset voltage is smaller than -v8, the sense amplifier circuit SA operates as if the offset voltage had increased by 2V8, and if the offset voltage is larger than -v8, the sense amplifier circuit SA operates as if the offset voltage had increased by 2V8. The sense amplifier circuit SA operates as if the voltage had decreased by 2V8. Therefore, the stochastic distribution of the offset voltage is from 13V to 3V.
Up to v8. Even within the range, the effective offset voltage operates as if distributed from -v8 to v,1. Therefore, assuming that the offset voltage distribution is constant, by using such a correction means, the signal voltage v8 from the memory cell can be reduced to approximately (), and the size of the memory cell can be reduced.

FIG. 6 shows a specific example of the correction circuit, in which the correction memory cell M is a field effect transistor Q. A flip-flop circuit consisting of a load resistor R1#R2 and a charge boost effect transistor for writing correction information to the flip-flop circuit using a clock signal (c) during the correction period. Furthermore, the signal generation circuit G includes field effect transistors Q.1, QO2,
QO3 and capacitor C1 are connected as shown in the figure, and clock signal φ is applied to node N. 1 to a constant potential, the transistor Q is activated by the clock signal φNK during the read period.
. 3 conducts, the content of the correction memory cell, that is, the potential of the node N (, 2), the node N.
The electrical connection with the Transistor Q. When capacitor c1 is controlled to be conductive, a correction voltage determined by the capacitance of capacitor c1 can be applied to bit line BL.

FIG. 7 shows another specific example of the correction circuit, in which the correction memory cell M' is a field effect transistor Q. , 0~QC1
The signal generating circuit G includes a field effect transistor Q to provide a correction capacitance to the bit line. 7 and a capacitor C2.

In the first embodiment, there are two correction circuits CL.

and Cl3 were used, but the second
The embodiment includes four correction circuits CL, Cl3. Cl3
．． Cl3, and a correction circuit CL1. Cl3
is BL, and correction circuit CL2. CL4 is bit line BL2
are connected to each. Correction circuit CL1. Just like CL2, the correction circuit CL3 (Cl3) is a signal generation circuit G.
3 (G4) and a correction memory cell M3 (M4), and the signal regeneration circuit G3 (G4) is controlled by the correction memory M3 (M4). Second
A correction period is also provided in the embodiment. In the first half of the correction period, the correction circuit C is operated in exactly the same manner as in the first embodiment.
L.

Information regarding the offset voltage is stored in Cl3, and the width of the effective offset voltage distribution is reduced by 4V8. In the second half of the correction period, the correction circuit CL.

and Cl3, the correction circuit CL3. Correction circuit CL to Cl3
, and information regarding the effective offset voltage corrected by Cl3. By using four correction circuits in this manner, the width of the offset voltage distribution can be effectively reduced by 8v8.

By further increasing the number of correction circuits, it is also possible to further effectively reduce the width of the offset voltage distribution.

In the above embodiment, the signal generating circuit G, @ G2 has the function of lowering the voltage of the bit lines BL, BL2 by a certain amount, but the signal generating circuit G, +02 has the function of lowering the voltage of the bit lines BL, BL2. Parasitic capacitance CB8. It may have a function of increasing CB□.

In the embodiments described above, the correction memory cells M, . . . M2 are so-called static memory cells, but they may also be dynamic memory cells or programmable ROMs.

In the case of dynamic memory cells, it is necessary to provide a periodic correction period even after the power is turned on, and programmable ROM
In this case, it is sufficient to provide only one post-manufacturing correction period.

In the first embodiment, the memory cell M at the beginning of the correction period. 1 and M. The node NM of N is set to O port, and then the sense amplifier circuit S is set to obtain correction data.
Immediately before operating A, the voltage difference between the two bit lines is v8.
was set to . Therefore, the offset voltage correction is
Correction is performed with respect to K only when the absolute value of the offset voltage is v8 or more, and no correction is performed when the absolute value of the offset voltage is slightly smaller than v8. However, there are stochastic variations in the signal output from the memory cell to the bit line, and there may also be manufacturing variations in the correction circuit, so correction is performed even if the absolute value of the offset voltage is slightly smaller than v8. The purpose of Honkotomei can be more reliably achieved if

FIG. 9 shows a row circuit of a third embodiment that is improved in this respect. The row circuit of the third embodiment is constructed by adding a field effect transistor Q1 to the row circuit of the first embodiment shown in FIG. 5, and the source and drain of the field effect transistor Q1 are connected to the bit lines BL1 and BL2. are connected to each other,
A clock signal φ1 is supplied to the gate of the transistor Q1. At the beginning of the correction period of the third embodiment,
First, the hit line BL BL is connected to the precharge circuit p
c,, pc2 is set to a higher voltage than 1 l 2 , and then the clock signal φ1 is set to a higher voltage. Next, a clock signal φ is supplied to the sense amplifier circuit SA. is set from high voltage to low voltage. At this time, since the clock signal φ1 is set to a high voltage, the bit lines BL and BL2 are electrically connected.
Even if the clock signal φ is set to a low voltage, the normal detection amplification operation is not performed, and both the hit lines BL and BL2 are connected to the clock signal φ. The voltage is set to the voltage plus the threshold voltage of the piezo field effect transistor. Clock signal φ. If the low voltage of is 0 port, the bit lines BL and BL2 are set to the threshold voltage K. At this time, memory cell M
If the word line connected to memory cells MC and MCN is maintained at a high voltage, the node NM between memory cells MC and MCN is set to the above threshold voltage. Thereafter, the clock signal φi is set to a low voltage again, and the bit lines BL1 and 'BL2 are set to a high voltage (2), just as in the first embodiment. , and then selects the memory cell MC1 and the dummy cell circuit DC2, the voltage difference between the bit lines BL and BL2 is set to a value smaller than vl (this value is called y/).

On the other hand, the amount of correction by the signal generation circuits G1 and G2 is also 2V;
By setting , it is possible to perform correction even when the absolute value of the offset voltage is smaller than v8.

In the above-mentioned third embodiment, only when operating the sense amplifier circuit for inspection during the correction period, the voltage of the signal from the memory cell is reduced compared to the normal read period. was set equal to the threshold voltage of the field effect transistor.

However, the key point is to set the bit line voltage to a value closer to the intermediate voltage vDD/2 than the write voltage to the memory cell during the normal write period (that is, 0 port and vDD in the example), and By setting the node NM of the cell K, it is possible to obtain a smaller signal voltage than in the read period.

By setting the σ bit line voltage in the third embodiment different from the write period, the voltage at the node NM of the memory cell was set, and a smaller signal amount than usual was obtained in the correction period. The above write voltage to the memory cell during the correction period is made equal to the normal write voltage, and after the refresh time of this memory circuit or a time longer than that has elapsed, the memory cell is selected and a smaller electrical signal than usual is applied to the bit line. obtained,
The sense amplifier circuit may be operated for testing purposes.

Also, in this case, by selecting a large number of memory cells one after another,
The sense amplifier circuit may be tested based on the electrical signal from the memory cell with the smallest amount of signal voltage.

As explained above, according to the present invention, the width of the offset voltage distribution of the sense amplifier circuit can be effectively reduced, the signal voltage output from the memory cell to the bit line can be reduced, and the memory cell can be made smaller. Therefore, according to the present invention, it is possible to increase the density of the memory circuit.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a row circuit of a conventional memory circuit, Figure 2 is a circuit diagram of a memory cell, Figure 3 is a circuit diagram of a dummy cell circuit, Figure 4 is a circuit diagram of a sense amplifier circuit, and Figure 5 is a circuit diagram of a dummy cell circuit. The configuration of the row circuit according to the first embodiment of the present invention, FIGS. 6 and 7 are circuit diagrams showing specific examples of the correction circuit, and FIG. 8 shows the configuration of the row circuit according to the second embodiment of the present invention. FIG. 9 is a block diagram of a row circuit according to a third embodiment of the present invention. MC, MC----゛...MC No. rMC! +11...
・・・MCN ・・・・・・・・・Memory
2' Cell, DC, IDc2... Tummy cell circuit,
SA・・・・・・Sense amplifier circuit, PCl,
PC2... Song/precharge circuit, DIO...
......Data input/output card--circuit, BL, IBL2..., upper soto line,
CM, CD・・・・・・・・・Capacitor, NMI
ND・・・・・・Node, VDDI v88...
...DC voltage, φ,, φ0. φ,...
...Clock signal, QM'QDI/Q81'
Q82' Ql ...... Field effect transistor, CL, I CL21 CL31 CL
4....--Correction circuit, G p G 21 G
3j G 4... Signal generation circuit, M1
2M2 M31 M4 ・・・・・・・・・Correction memory cell.

Claims (2)

[Claims] (1) Equipped with a large number of memory cells (referred to as main memory cells) for storing information input from the outside, and equipped with a sense amplifier circuit for detecting electrical signals output from the main memory cells. In the memory circuit, a J-Moly cell (referred to as a correction memory cell) other than the above that stores information for correcting the sense amplifier circuit, and a memory cell for correcting the sense amplifier circuit based on the information stored in the correction memory cell. means for correcting the operation; and means for operating the sense amplifier circuit while inputting an electrical signal output from the main memory cell to the sense amplifier circuit to obtain information stored in the correction memory cell. A memory circuit characterized in that: (2) The means for obtaining the information to be stored in the correction memory cell is configured to obtain 2 which is applied to the storage node of the main memory cell in response to two logical values when externally input information is input to the main memory cell. By creating a voltage lower than one of the seed voltages and higher than the other at the storage node of the main memory cell and outputting an electrical signal from the main memory cell to the sense amplifier circuit, the voltage stored in the correction memory cell is The memory circuit according to claim 1, characterized in that the memory circuit is configured to obtain information.