JPS58104550A - Line selection system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rigid line selection method in a telemeter system that collects data from a large number of slave stations to a master station via a star line and performs intensive Il viewing.

In the Telemake 7 system, which uses a centralized monitoring system that is distributed in a distributed manner* and collects data from N slave stations to the master station via a star-shaped mat-, data is collected by sequentially polling the slave N4 from the master station. The method of doing this is generally adopted.

No. 11O conceptually shows a central monitoring telemeter system. In Figure fj1, i shows the muhiro master station, that is, the centralized monitoring and control device, and Jh+J1m+...
1% indicates N slave stations, that is, monitored control devices. The master station A and the slave stations J+, J1+..., Js are connected to each other through a star-shaped circuit, and the master station A is called and called sequentially through each slave station. Polling-based data collection is performed by sending data from the 9th station back to the 7/11 data station.

1 in a telemeter system with a 1:N configuration
In ijl, it is common practice to use only one modulator/demodulator (t-1) for economic reasons, and to connect the line by branching (i) once using the liA branch. Furthermore, - line segment wi like this
The circuit is often divided into a plurality of units due to physical constraints in pigeon coops with a large number of wires.

The second Ii shows the configuration of ItM. In the same figure,
Reference numeral 1 denotes a transmission control device consisting of a microprocessor. What about 2? Jl/Jl p conversion circuit, which performs mutual conversion between a parallel signal in transmission control and a serial signal in garden-even, where i is modulation/demodulation and p
The serial signal of s7spgR switch 2 and the carrier signal in one chain are mutually transformed.

4-1+4-1+......+ 4-s is a line branching unit that converts 11 times 6 serial data [each from multiple (Z, 1 to L)]
-+, 5-z, . 6 is a control bus, and 7 is a 7dress data bus, which connects the transmission control device 1 and ps/sp conversion.
Route 2 and circuit branch unit '-f+4-2g...
. . , 41, transmits control signals, line addresses, and data, respectively.

In this way, a large number of (b) lines are accommodated separately in multiple line branching units, and the transmission control device consisting of a microprocessor transmits line switching information to the bus of the microprocessor and sends it to the branching unit. is configured to print.

[Figure 13 shows the operation timing when the line selection data is written to the branch unit by the address/data bus and control bus in the master station. In the same figure, (A) indicates the timing of No. 411 and 5(j)F
i, the transmission direction of each corresponding signal [indicated]. (・) indicates an address, and (&) indicates data.
The information is transmitted from the transmission control device to the link/branch unit via the data bus.

(-) instructs the line branch unit to fold the address and data.Write II number WλT1(2) indicates that the address and data are on the bus K11ji! A strobe signal sYo indicative of the fact that the line has changed is also transmitted from the transmission control device to the line branching unit via the control bus. (-) is the response signal IVI that is sent back to the transmission control device via the dynamic control bus when the signal SVO is received by the line branching unit, and is the output time of the address in the 11m5 branching unit. - Output is delayed.

In this way, when writing the 11 selection data from the transmission control device to the line branching unit, it takes t10 sessions to determine which (9) branching unit the number (B) is stored in. Miyako*gsen will be responsible for processing the Procera fee [
This is undesirable because of the risk of increasing the number of lines.Assuming that the addresses of all branch units are the same, the upper seven bits of one line group are used to identify the line group that belongs to that unit on the branch unit side. ing.

The configuration of the 4th line selection data is as follows: 8 uniform branching units are used for one line #, 1lQ for 5-nits.
The case of accommodating Il is shown as an example. In the same figure,
The lower six bits (D10 to J)15 of the data are sent to the computer and written to the line branching unit as binary data. Therefore, in the case of this example, selections up to 641i1i1 are possible. In addition, the top 1 data in %#E411
0 bit is an invalid day! It is. Of the 6 bits of valid data, the upper 5 bits D10 to D12 are used to determine the (b) branch unit t-m as the group address of the line accommodated in one bundled branch unit).
Bits D15 to D15 are used as a set of selection signals within the unit.

Figure jI5 shows the -1 selection method of pawn in K. In 11, 11 is a unit address comparator, which receives a write signal WIIT from the transmission control device.
When the strobe signal 1ivo Vr reception is good, the address of the line branch unit on the address bus is set in the address setting 11112, and the i-address and t are compared.
- When the address is entered, the address signal is sent. 1s line group selection section, upper 3 bits of line selection data
)jHO~J)12 is compared with the Mll group address i set in the group setting unit 14, and if they match, a friend and group return signal tm is generated. 15←AND circuit, and a set of the logical product of the address -am and the group signal is generated. The logical product signal is sent back to the transmission control device as a response signal SYI, and is also given to the latch circuit 16 as a clock signal. Latch enclosure 14i
jThe clock value number is received in the hole, and the lower 3 of the drawing selection data
Pitsu) D15 to D15 i Latch and output.

17 is a decoder 6 which decodes the output data of the latch circuit 16 and outputs each decoy selection note LO to L7 for 11 once.

By using this method of selection, even if the addresses for multiple four-wire classification units are the same, the required line branching unit and (8) You can choose at,
The answer signal 11VI is never returned from more than one m-branch unit at the same time.

However, in the case of the 9th system shown in sswA, when multiple branch units are used, the data in the latch circuit is not rewritten, so in the 11th branch unit, the data that has already been loaded is The uniformity selection signal continues to be generated from the decoder depending on the data. Therefore, the selected 4-branch unit 4 is not selected (b)-
Since the branch unit also has one line connected to each unit, for example, when the branch unit has 96 units as shown in tjN4E and FIG. 5, 8 (b) lines are connected to form a hole 11. In such a situation, the noise on the 6 receivers is added together and received by the master station. Therefore, if the uniform S//N ratio is poor, the data gAJ rate will deteriorate.

The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to write the selected data into one IilIII branch unit by writing the line, and the other units write the (9) line. Make it so that selection is prohibited,
Only 11 lines are selected from the total number of lines accommodated, so that multiple lines and strings can be selected. The objective is to provide a system that does not cause a deterioration of the rental ratio even if the cables are connected.

Hereinafter, the present invention will be described in detail with reference to additional examples.

Figure 6 shows the configuration of an embodiment of the line selection method of the present invention:
It shows. In IIK, the same partial enlarged numbers as in GSG are shown, 18 is a delay circuit, and 19 is an inverter.

In the sixth EIIC, it is assumed that the same address is set for all the addresses in the - line branch unit, and the address of the branch unit is written through the address bus, and the write signal WET and strobe signal SVO are sent through the control bus. When a write is missed, an address intermittently is generated from the unit address ratio function section 11 in all the branch units.

On the other hand, the negative group selection section 15d selects the upper three bits of the E line selection data [9FjAl set in the group setting section 14].
Compared with the iA group address, it generates 9 and 1k1.

The address signal is applied as a clock signal to the latch @j114, thereby latching the lower five bits (DlS-j)15 and the group (intermittent) of the circuit selection data. 1, the address 歇子 and the group 歇儒 are logically ANDed in the AND wAj 115, and a response signal is sent via the output signal 织ENEN-路 18t-! It is returned to the transmission control device as an iVI. Therefore, the response signal 11VI may be sent back from multiple QJII branch units at the same time.
o Expansion, same as in the conventional method.

In this on-the-spot transmission control device, the strobe signal SYO disappears immediately after the response signal SVI is returned.

The output time t of the address - Qin's number is spread by p%.
Therefore, if the output time of the selected optical unit is the shortest, the other units will not be rewritten in the same line selection data D13-D15 and the Darubu intermittent latch circuit. omnibus ji
118 delays and returns the response signal 11VItyl for a time corresponding to the difference between the output times to in each unit, thereby ensuring that the data in each latch circuit is always updated.

(b) When -ik is obtained in the group selection section 15, the group selection signal "1" is generated and the latch is pressed. The output of the latch circuit passes through the inverter 19 and is written as the decoder 170 input At1C"Q'". In addition, in the unselected group (y), the group number is output as "0" and latched, so "1" is written into the input A of the decoder 17 via the inverter 19'.

Diagram 7 shows the input logic and output logic in the decoder 17. As seen in IIK, one-man power A is “0”
”, one of the outputs LO to L7 becomes “1” depending on the state of inputs B-D, which causes the corresponding 1
m1 is selected. On the other hand, when the input A is "1", the outputs LO to L71d are all "D", and therefore no four-line selection is performed.

As described above, in the line selection method of the present invention, the group-to-intermittent signal status imt times! iI is latched together with the selection data, and the output of the decoder is controlled according to the state of the latched group matching signal so that the Vk line branching unit that is not selected becomes the select-prohibited state. The belonging circuits m are never connected in parallel.

As mentioned above in IIMN, according to the line selection method of the present invention, the four belonging to each line segment unit are connected in parallel, so that the noise in each figure is not added. Even in the case of wires with extremely poor S/N ratios, high-quality data transmission can be achieved, making it extremely effective.

[Brief explanation of drawings]

Fig. 1 is a conceptual explanatory diagram showing a centralized monitoring telemeter system, a water diagram showing the configuration of a 1m2 diagram, and Fig. S is a diagram showing the operation timing when writing line selection data.
#I4 is a diagram showing the configuration of line selection data, Figure 185 is a block diagram showing a conventional line selection method, and Figure 6 is a block diagram showing the configuration of an embodiment of the line selection method of the present invention
Input logic and output logic in g711Fi decoder [
FIG. 1: Transmission control device, 2: 18/8F conversion path, 3:
14 variable circuits, 4-1+ +-2,"+ 4-s:
m line segment wrinkle unit, 5-1+ 5-2+・・・・・・+
5-11: Line, 6: 1111 control bus, 7: 7
)"Response data bus, 11: Unit address comparison section, 12: Address setting section, 13: IQ-group selection section, 14 Nigel group setting section, 15: AND circuit <AND)
, 16: Latch circuit, 17: Decoder, 18: Delay circuit, 19: Inverter (INV) Figure 1 Figure 3 Figure 2 Figure 4 Line number (BINARY) Figure 5 Figure 1 to Figure 7

Claims (1)

[Claims] A plurality of single branch units are selected by the same address from the transmission control device, and a plurality of single branch units belonging to each branch unit are selected by (b) one number data from the transmission control device. In the rigid line selection method that selects 1 (9) me from the main and controls both, a part of the 5tII data and the preset 9-group address match, and 9 and the self-guru-gu-kin-sho issue are generated. - means for generating an address signal when the address of the branch unit and a preset large address are part of each other; Remaining data [Latch 'PR'
and means for decoding the latched data and generating the same line selection signal when the group-1 ui4# is raised and the latched data is decoded to generate a same line selection signal, and the selected line 1ui4# is connected to a line other than the 11-minute block unit to which the 9@ line belongs. IIjt unit is wA-selection prohibition jin and t% mold is time-selection method.