JPS58101346A - Instruction execution controlling system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention provides an instruction execution control method, in particular, an instruction that executes instructions that can be overtaken regardless of the order of execution, ignoring the order of execution as far as possible. Instructions that cannot be overtaken are executed while maintaining the correct order.9 In a data processing system, a read instruction whose read operand address is the same as the write operand address for a previously fetched write instruction is extracted. This invention relates to an instruction execution control system in which execution of a write command is waited for in response to a dead read command, and execution of the write command is performed as much as possible to improve processing efficiency.

(2) Technical background and problems For example, in a data processing system that has the function of performing vector operations, there are a mixture of instructions that can be executed by overtaking the previous instruction, and instructions that may cause logical contradictions if executed by overtaking the previous instruction. Therefore, in order to improve processing efficiency, a method is adopted in which executable instructions are executed.

That is, for example, when there is a write instruction A that sets data in a register, and a read instruction B that reads the contents of the register follows, the above instruction is executed after waiting for the instruction person to complete the processing. It is necessary to perform B. In such a case, it is possible for the instruction C, which is located after the instruction A and before the instruction B, to be executed before the instruction person, but the instruction B must be executed after the instruction person has executed it. Conventionally, the instructions subsequent to instruction B have been made to wait until the execution of instruction A is completed.

(3) Purpose and structure of the invention The present invention aims to solve the above points,
Correctly extract only the above instruction B and make it standby, then instruction C-? Regarding D, the purpose is to provide an instruction execution control system that executes instructions to the extent possible. Therefore, the instruction execution control method of the present invention fetches a plurality of instructions, ignores the order of instructions that can be overtaken regardless of the order, and executes them in the order of possible instructions. For non-overtaking instructions that require context, in a data processing system that is controlled to wait for the execution of the previous instruction and then start the execution of the next instruction, during a write instruction in instructions that are fetched sequentially. The write value is Rand.
The write address that stores the address is a land address holding unit, the collation processing unit that matches the read address in the next fetched read command and the contents of the write address land address holding unit O, and the fetch is performed sequentially. A group of instruction registers that stores incoming instructions and sets and stores an execution prohibition flag for read instructions that are found to be a match in the collation processing unit; An instruction transmission control unit that extracts unprocessed instructions and supplies them to the arithmetic execution unit, and a corresponding execution prohibition flag in the instruction register group when the write instruction that caused the execution prohibition flag to be set is executed. The present invention is equipped with an off control unit that turns off the t-
It is a feature. This will be explained below with reference to the drawings.

(4) Embodiment of the Invention FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows a main part configuration of an embodiment of an instruction control device shown in FIG.

In FIG. 1, 1 is a main memory device, 2 is a main memory control device that performs intermediary processing to access the main memory 1t, and 3 is an instruction control device that fetches instructions from the main memory device and executes calculations. What is sent as a command to the device,
Reference numeral 4 represents an arithmetic execution unit which receives and processes instructions, 5 represents an instruction buffer in which fetched instructions are temporarily set, and 6 Fi instruction registers.

In the case shown in FIG. 1, the instruction is fetched by either the main memory 1 or the instruction control device 3, and is stored in the instruction register group 6 with an execution prohibition flag Ct added as necessary, as shown in FIG. be done.

The instruction control device 3 extracts executable instructions for which the execution prohibition flag C is not set and supplies them to the arithmetic execution device 4. The arithmetic execution device 1 executes the supplied instruction and notifies the instruction control device 3 of the completion of execution.

As a result, as will be described later with reference to FIG. 2, when the execution of the instruction that caused the execution prohibition flag C1 to be set is completed, the instruction control device 3 turns off the execution prohibition flag Ct and cancels the execution suspension. I'll do what I do.

In Figure 2, the number 6 corresponds to Figure 1, and F is the command.
Reference numeral 8 designates an instruction fetch control unit which fetches instructions from the instruction buffer 5 shown in FIG. 4 and 11 are land address holding registers, 12 and 13 are address verification processing units, and 14 is an instruction transmission control unit. Instructions for which the execution prohibition flag is not set are selectively taken out from the instruction register group 6 and sent to the arithmetic execution unit 4. 0116 is a selector and a validity indication bit vt is set for the selected instruction.
- Invalid control: 16 to 20 are AND circuits, and 21 is an OR circuit. Note that the flip-flop 10 constitutes an OFF control section according to the present invention.

The instruction fetch control unit 8 performs control to sequentially fetch instructions from the instruction buffer 5 shown in FIG. The command is Oi code opa moth and write Oi land address R1
It is assumed that the memory area has a read O land address R2 area, and a read O land address R3 area. The instruction fetched by the instruction fetch control section 8 is set in the instruction register group 6, and the instruction decoding section 9 decodes the contents of the offer code OP*. If the instruction is a write instruction, the flip e-flop 10 is set, and the write address of the instruction is such that the contents of the address R1 area in the land are stored in the register 11.
is set to

Under this state, instructions are fetched from the instruction fetch control unit, and if these instructions are read instructions, they are stored in the instruction register group 6, and
The contents of the read operand address R2 area and the contents of the R3 area are stored in the register 1 by the matching processing units 12 and 13, respectively.
It is compared with the contents of 1. Which collation processing unit 12.13
If no matching output is generated from the AND circuit 21, the AND circuit 1j and 19t are turned on, but the OR circuit 21 generates the logic 11rOJ, and the execution prohibition flag C is not turned on. , However, if a matching output occurs in either matching processing section 12 or 13,
The OR circuit 21 issues a logic rlJt- and sets an execution end flag C for the read instruction.

When the instruction fetch control unit 8 outputs a write instruction t- with the flip-flop 10 set, the AND circuit 16 is turned on and the subsequent instruction fetch tlII! The write command is held in the command fetch control section 8.

On the other hand, the instruction transmission control unit 14 extracts an instruction whose validity indication pin (V) indicates validity from the instruction register group 6 and for which the above-mentioned execution prohibition flag C is not set. ), and supplies it to the arithmetic execution unit number. Then, the retrieved instruction is switched to Vt invalid (beep).

The arithmetic execution unit 4 executes the supplied instruction and then notifies the user when it finishes executing the write instruction. As a result, the clip number flop lO is reset, and all execution prohibition flags Ct set in the instruction register details 6 are turned off. That is, instructions that were prohibited to be executed are switched to executable, and those instructions are supplied to the arithmetic execution unit number. On the other hand, the AND circuit 16 is turned off, and the write command held in the instruction fetch control section 8 is stored in the instruction register group 6 and a value is set in the register 11. Hereinafter, the format will be the same as in the case where the write command is taken out first.

In the above embodiment, only a single write instruction is stored in the instruction register group 6, but by having flip-flops 10, registers 11, etc. redundantly, multiple write instructions can be stored in the instruction register group 6. 6 is optional.

(5) As described in detail, according to the present invention, it is possible to correctly extract only the instructions that cannot be overtaken, and also to select the instructions and set the execution prohibition flag C. . Therefore, according to the present invention, it is possible to perform overtaking depth also in response to the command described in the above-mentioned "Technical Background and Problems."

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a data processing system to which the present invention is applied, and FIG. 2 shows a main part configuration of an embodiment of the instruction control device shown in FIG. In the figure, l is a main storage device, 3 is an instruction control unit, 4 is an arithmetic execution unit, 5 is an instruction buffer, 6 is an instruction series group, f is an instruction, 8 is an instruction fetch control unit, 9 is an instruction decoding unit, lO
11 is a slip flop that constitutes an off control section; 11 is a write address holding register;
Reference numerals 12 and 13 represent an address verification processing unit, and 14 represents an instruction transmission control unit. Patent applicant Fujitsu Ltd. Representative Patent Attorney Mori 1) Hiroshi (1 other person) 1 year old

Claims (1)

[Claims] When a plurality of instructions are fetched, instructions that can be overtaken regardless of the order of the commands are executed starting from those that can be executed regardless of the order, and instructions that cannot be overtaken regardless of the order of the commands are executed. In a data processing system where instructions are controlled to wait for the execution of the previous instruction before starting the execution of the next instruction, the write operand address in the write instruction in the name instruction is fetched sequentially. a write operand address holding unit that stores
The read instruction in the next fetched and delayed read instruction holds the land address and the write operand 1 address, is fetched sequentially, is stored on the next instruction, and is executed for the read instruction that matches in the matching processing section. A group of instruction registers that set and store a prohibition flag; an instruction transmission control unit that extracts instructions for which the execution territory flag is not set among instructions in the instruction register group and supplies them to an arithmetic execution unit; an off control unit that turns off the execution prohibition flag in the instruction register group when the write instruction that caused the flag to be set is executed;
This is an instruction depth control method in which instructions that can be overtaken and executed are overtaken and instructions that cannot be overtaken are maintained in the execution order.