JPS581002Y2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device that generates communication speed timing for connecting to a communication line in the communication control device.

When performing data communication over a communication line, a communication control device must send out transmission data to the communication line and receive received data from the communication line at a communication speed predetermined for the communication line.

Communication speed timing may be provided by a modem or may be generated by a communication controller.

Conventionally, in communication control equipment, the output of an oscillator is divided by a frequency dividing circuit with a fixed frequency division value, several types of standard communication speed timings are prepared, and the timing is set by hardware jumper wiring or program specification. One of these was selected to obtain the required communication speed timing.

This device has the disadvantage that when a communication speed other than the predetermined communication speed is required, the oscillation frequency of the oscillator or the frequency dividing circuit, etc., must be changed.

The purpose of this invention is to provide a communication control device that does not require any hardware changes even in response to various communication speed requirements.

According to the present invention, the output of the oscillator having the maximum required frequency or a higher frequency is divided by the frequency dividing circuit.

The output of this frequency dividing circuit is used as a timing output, and the frequency dividing circuit is set to an initial value.

This initial value is stored in a register in advance, but it can also be stored in a program and set as desired.

In this way, an arbitrary communication speed timing can be obtained within the setting error range without changing the hardware, and a highly flexible communication control device can be obtained.

Next, a description will be given with reference to the drawings.

FIG. 1 shows an example of a communication control device according to this invention, in which a transmission shift register circuit 1 converts parallel signals into serial signals, and a transmission character transferred from a transmission buffer register circuit 2 is transferred to a communication speed timing generation circuit. Characters are decomposed according to the communication speed timing from 3 and transmitted to the communication line 4a one bit at a time.

The transmission buffer register circuit 2 is a buffer for character transfer interposed between the transmission shift register circuit 1 and the central processing unit 5.

On the other hand, the data received from the communication line 4b is received bit by bit by the reception shift register circuit 6 according to the communication speed timing from the communication speed timing generation circuit 3, and character assembly is performed, that is, serial-parallel conversion is performed to assemble the character. The completed data is transferred to the reception buffer register circuit I, which is a buffer for character transfer with the central processing unit 5.

The communication speed timing generation circuit 3 generates the required communication speed timing, the control circuit 8 performs communication control processing, and the transfer control circuit 9 controls the buffer register circuits 2 and 7.
and the central processing unit 5.

A communication speed timing generation circuit 3 used in a conventional communication control device is composed of an oscillator A, a frequency dividing circuit B, and a 1/2 frequency dividing circuit C, as shown in FIG.

Output signal a from oscillator A is frequency-divided by frequency divider circuit B.

From the appropriate division stage of frequency divider circuit B, a signal corresponding to standard communication speed timing is taken.

In the figure, for convenience, there are three types of signals, c) and d, which are obtained at terminals 10a, 10b, and 10c, respectively.

When the communication speed is determined, bye. A corresponding terminal among the terminals d is selected by a jumper wire e, and is manually inputted to a 1/2 frequency divider circuit C to obtain a required communication speed timing signal f as its output.

The 1/2 frequency divider circuit C has a timing duty cycle of 5.
This is to make it 0%.

This conventional communication speed timing generation circuit uses a timing signal.

If a communication speed other than c or d is required, change the oscillator A to change the frequency of its output signal a, or change the frequency divider circuit B to change the frequency of the signals c) or d. There was a need.

Such changes were also extremely inconvenient.

On the other hand, the communication speed timing generation circuit used in the communication control device of this invention uses an oscillator A as shown in FIG.
, an n-bit counter B whose initial value can be set, a 1/2 frequency divider circuit C1 initial value set control circuit D, and an initial value setting n-bit register E.

When the communication speed is determined, an initial count value (xO to XH-1) corresponding to the complement of the required frequency division count value to the counting capacity of counter B is set in register E by strobe signal e.

In addition, an initial value set signal d is generated from the control circuit by the trigger of the signal e, and the initial count value XO to Xn-1' set in the register E by this signal d is set in the counter B.

Counter B counts the output signal a of oscillator A, and outputs a carry signal when an overflow occurs.

The carry signal is frequency-divided through a 1/2 frequency divider circuit C to obtain the required communication speed timing C.

The carry signal is also supplied to the control circuit, which generates the initial value set signal d again, resets the initial count value (XO~xn-1>) in the counter B, and outputs the output signal a.
The count is cascaded, and the communication speed timing continues to occur.

By changing the initial values XO to Xn-1 set in the register E, various communication speed timings can be obtained.

The initial values for obtaining the required communication speed timing are the oscillation frequency of the oscillator (frequency of output signal a) and the counter B.
, the number of bits n of register E.

The range of achievable communication speeds is limited by the oscillation frequency of the oscillator and the number of bits of the counter B register E.

The error in communication speed timing is calculated from the oscillation frequency and deviation of oscillator A, the number of bits of counter B and register E, and the required communication speed.

As mentioned above, the oscillation frequency of oscillator A and counter B
, by appropriately setting the number of bits n of register E, the desired communication speed timing can be obtained by simply changing the initial value using the program, eliminating the need to change the hardware and making the change extremely easy. Become.

Therefore, it is possible to obtain a communication control device that is highly flexible in selecting communication speed timing.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a communication control device according to the invention, and Fig. 2 is a block diagram showing a communication speed timing generation circuit used in a conventional communication control device. , FIG. 3 is a block diagram showing an embodiment of a communication speed timing generation circuit used in a communication control device according to the present invention. A: Oscillator, B: Counter.

Claims (1)

[Scope of utility model registration request] a serial-to-parallel conversion unit that performs serial-to-parallel conversion of transfer data to control data transfer between a communication line and a data processing device; a communication control unit that operates according to a processing request from the data processing device and the serial-to-parallel conversion unit; In the communication control device, the communication control device includes a transfer control unit that transfers information to and from the device, and a communication speed timing generation unit that supplies the serial-to-parallel converter with a communication speed (beep 17 seconds) of information with the communication line. The communication speed timing generator includes an oscillator and a counter that can count the output of the oscillator and set an initial value.
a register connected in parallel to the counter to which an arbitrary value can be set; means for setting the value set in the register by a carry output of the counter to the counter as an initial value; and a carry output of the counter. A communication control device comprising a frequency dividing circuit which divides the frequency by seven, and obtaining communication speed timing from the output of the frequency dividing circuit.