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JPS5797234A - Output setting circuit for charge pump - Google Patents

Output setting circuit for charge pump

Info

Publication number
JPS5797234A
JPS5797234A JP55173713A JP17371380A JPS5797234A JP S5797234 A JPS5797234 A JP S5797234A JP 55173713 A JP55173713 A JP 55173713A JP 17371380 A JP17371380 A JP 17371380A JP S5797234 A JPS5797234 A JP S5797234A
Authority
JP
Japan
Prior art keywords
output
phase comparator
divider
charge pump
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55173713A
Other languages
Japanese (ja)
Inventor
Toshiyuki Ozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP55173713A priority Critical patent/JPS5797234A/en
Publication of JPS5797234A publication Critical patent/JPS5797234A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To reduce power consumption, by turning off a transistor of a charge pump, through the interruption of a frequency division output of a voltage- controlled oscillating circuit or a reference signal at the off-state of power supply and applying a control signal to a phase comparator. CONSTITUTION:A PLL circuit consists of a programmable divider 1, a voltage controlled oscillator 2, a reference divider 3, a reference oscillator 4, a phase comparator 5, charge pump 6, and a low pass filter 9. The output of the divider 3 is applied to the phase comparator 5 via an AND11 and an OR12. A control terminal 15 is at an H level at the on-state of power supply and at L level at a backup(off)-state, the AND11 interrupts the output of the divider 3 and a high level signal is applied to a -input of the OR12 via an inverter 13 and a delay circuit 14, an output U of the phase comparator 5 is made to an H level and a transistor 7 is turned off.
JP55173713A 1980-12-08 1980-12-08 Output setting circuit for charge pump Pending JPS5797234A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173713A JPS5797234A (en) 1980-12-08 1980-12-08 Output setting circuit for charge pump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173713A JPS5797234A (en) 1980-12-08 1980-12-08 Output setting circuit for charge pump

Publications (1)

Publication Number Publication Date
JPS5797234A true JPS5797234A (en) 1982-06-16

Family

ID=15965745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173713A Pending JPS5797234A (en) 1980-12-08 1980-12-08 Output setting circuit for charge pump

Country Status (1)

Country Link
JP (1) JPS5797234A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608463A (en) * 1992-08-26 1997-03-04 Nec Corporation Oscillator circuit suitable for picture-in-picture system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608463A (en) * 1992-08-26 1997-03-04 Nec Corporation Oscillator circuit suitable for picture-in-picture system

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