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JPS5796562A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5796562A
JPS5796562A JP55173521A JP17352180A JPS5796562A JP S5796562 A JPS5796562 A JP S5796562A JP 55173521 A JP55173521 A JP 55173521A JP 17352180 A JP17352180 A JP 17352180A JP S5796562 A JPS5796562 A JP S5796562A
Authority
JP
Japan
Prior art keywords
corners
supporting frame
pellet
lead
hangers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55173521A
Other languages
Japanese (ja)
Other versions
JPS6134254B2 (en
Inventor
Takashi Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55173521A priority Critical patent/JPS5796562A/en
Publication of JPS5796562A publication Critical patent/JPS5796562A/en
Publication of JPS6134254B2 publication Critical patent/JPS6134254B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To match the connection of a lead easily aligned, and to insert a semiconductor pellet accurately by removing frame hangers at four corners from the side inner than a square surrounded by the four corners of a supporting frame when the pellet is cut from a tape and inserted into a cavity in a case. CONSTITUTION:The frame hangers at four corners are punched by means of a punch according to a tape carrier system. Even when the hangers are punched at that time, the semiconductor pellet 3 does not slip off because the supporting frame 7 and the pellet are connected to the tape 1 by the lead 5. Accordingly, escapes 15 are formed at the four corners of the supporting frame 7. The semiconductor pellet 3 is cut, and incorporated into the case 9. The whole supporting frame 7 is encased into the cavity 10, and a terminal of the lead 5 and an internal terminal 13 contact. Consequently, connection is easily aligned, and the displacement of contact is prevented.
JP55173521A 1980-12-09 1980-12-09 Semiconductor device and manufacture thereof Granted JPS5796562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173521A JPS5796562A (en) 1980-12-09 1980-12-09 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173521A JPS5796562A (en) 1980-12-09 1980-12-09 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS5796562A true JPS5796562A (en) 1982-06-15
JPS6134254B2 JPS6134254B2 (en) 1986-08-06

Family

ID=15962062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173521A Granted JPS5796562A (en) 1980-12-09 1980-12-09 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5796562A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188251A (en) * 1986-02-13 1987-08-17 Nec Corp Mounting structure of integrated circuit
US4890152A (en) * 1986-02-14 1989-12-26 Matsushita Electric Works, Ltd. Plastic molded chip carrier package and method of fabricating the same
JPH02163949A (en) * 1988-12-17 1990-06-25 Ibiden Co Ltd Substrate for semiconductor mounting use

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232267A (en) * 1975-09-05 1977-03-11 Citizen Watch Co Ltd Ic packaging construction

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232267A (en) * 1975-09-05 1977-03-11 Citizen Watch Co Ltd Ic packaging construction

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188251A (en) * 1986-02-13 1987-08-17 Nec Corp Mounting structure of integrated circuit
US4890152A (en) * 1986-02-14 1989-12-26 Matsushita Electric Works, Ltd. Plastic molded chip carrier package and method of fabricating the same
JPH02163949A (en) * 1988-12-17 1990-06-25 Ibiden Co Ltd Substrate for semiconductor mounting use

Also Published As

Publication number Publication date
JPS6134254B2 (en) 1986-08-06

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