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JPS5795654A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5795654A
JPS5795654A JP17129680A JP17129680A JPS5795654A JP S5795654 A JPS5795654 A JP S5795654A JP 17129680 A JP17129680 A JP 17129680A JP 17129680 A JP17129680 A JP 17129680A JP S5795654 A JPS5795654 A JP S5795654A
Authority
JP
Japan
Prior art keywords
leads
pair
lead
parallel
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17129680A
Other languages
Japanese (ja)
Other versions
JPS6050357B2 (en
Inventor
Shinzo Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55171296A priority Critical patent/JPS6050357B2/en
Publication of JPS5795654A publication Critical patent/JPS5795654A/en
Publication of JPS6050357B2 publication Critical patent/JPS6050357B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To prevent the mutual contact of each lead pair by a method wherein a pair of leads are formed at the symmetrical positions of both ends while being vertically bent to the surface of a chip, a connecting plate is spanned crossing the leads and connection with the outside is facilitated, and each lead pair is arranged in parallel. CONSTITUTION:A pair of the electrode leads 12a, 12b are erected at the symmetrical positions of both ends to the main surface of the semiconductor chip 11, the leads 13a, 13b are mounted similarly, and straight lines connecting the terminals of each pair are mutually disposed in parallel. A small wire is used as a lead 14 for a control electrode in accordance with a conventional method. The connectng plates 12e, 13e are laid over the leads 12a-12b, 13a-13b and one ends are connected to printing conductors 16a, 16b on a substrate 15, and the lead 14 is connected to a conductor 16c. The other ends 12d, 13d are connected to external power supplies or load or the like. According to this constitution, the connecting plates run parallel mutually and do not contact each other, and forced stress does not apply to the semiconductor chip.
JP55171296A 1980-12-04 1980-12-04 semiconductor equipment Expired JPS6050357B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55171296A JPS6050357B2 (en) 1980-12-04 1980-12-04 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55171296A JPS6050357B2 (en) 1980-12-04 1980-12-04 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5795654A true JPS5795654A (en) 1982-06-14
JPS6050357B2 JPS6050357B2 (en) 1985-11-08

Family

ID=15920661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55171296A Expired JPS6050357B2 (en) 1980-12-04 1980-12-04 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6050357B2 (en)

Also Published As

Publication number Publication date
JPS6050357B2 (en) 1985-11-08

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