JPS5786195A - Protecting circuit for data in memory - Google Patents
Protecting circuit for data in memoryInfo
- Publication number
- JPS5786195A JPS5786195A JP55160369A JP16036980A JPS5786195A JP S5786195 A JPS5786195 A JP S5786195A JP 55160369 A JP55160369 A JP 55160369A JP 16036980 A JP16036980 A JP 16036980A JP S5786195 A JPS5786195 A JP S5786195A
- Authority
- JP
- Japan
- Prior art keywords
- data
- line
- level
- address
- write pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Abstract
PURPOSE:To prevent data in a random access memory from being erased owing to the runaway of a program itself, by protecting the data in the random access memory corresponding to every address. CONSTITUTION:In loading mode, a mode line 5 and a reset line 6 are held at levels H, and an address specified by an address line 12 is used to write data from a data bus 29 in an RAM1 and a 1 is written from a data input line 10 in control memory 2. Then, data from the RAM1 is written in the corresponding address of the control memory 2 to set writing inhibition. In work mode, the mode line 5 is held at a level L and the reset line 6 stays at the level H; and a write pulse control circuit 3 exercises control to send a write pulse to a write pulse input line 8 when the data has the level L, but to send no write pulse when the data has the level H.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55160369A JPS5786195A (en) | 1980-11-14 | 1980-11-14 | Protecting circuit for data in memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55160369A JPS5786195A (en) | 1980-11-14 | 1980-11-14 | Protecting circuit for data in memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5786195A true JPS5786195A (en) | 1982-05-29 |
Family
ID=15713479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55160369A Pending JPS5786195A (en) | 1980-11-14 | 1980-11-14 | Protecting circuit for data in memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5786195A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS601301U (en) * | 1983-06-06 | 1985-01-08 | 株式会社 力王 | underground |
-
1980
- 1980-11-14 JP JP55160369A patent/JPS5786195A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS601301U (en) * | 1983-06-06 | 1985-01-08 | 株式会社 力王 | underground |
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