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JPS5768916A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS5768916A
JPS5768916A JP14545780A JP14545780A JPS5768916A JP S5768916 A JPS5768916 A JP S5768916A JP 14545780 A JP14545780 A JP 14545780A JP 14545780 A JP14545780 A JP 14545780A JP S5768916 A JPS5768916 A JP S5768916A
Authority
JP
Japan
Prior art keywords
circuit
delay
signal
input signal
alpha
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14545780A
Other languages
Japanese (ja)
Inventor
Tadahiko Yanajima
Shinichi Amamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14545780A priority Critical patent/JPS5768916A/en
Publication of JPS5768916A publication Critical patent/JPS5768916A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30—Time-delay networks

Landscapes

  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To simply obtain a wide variety of variable delay time, by forming a delay circuit through the combination of delay elements and a weighted circuit. CONSTITUTION:An input signal Vi is branched: one is multiplied with a rate (1-alpha) at a weighting circuit 6, and another is delayed with a delay element 7 in delay time T. After a delay signal from the delay element 7 is multiplied with the rate alpha at a weighting circuit 8, it is applied to an addition circuit 9, where it is added with a signal from the weighting circuit 6. Thus, the added output signal of the addition circuit 9 is delayed by a time of about alphaT to the input signal Vi by forming the delay circuit to obtain almost the same amplitude signal with the input signal Vi. Then, a wide range of variable delay time can be obtained simply by varying the rate alpha.
JP14545780A 1980-10-17 1980-10-17 Delay circuit Pending JPS5768916A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14545780A JPS5768916A (en) 1980-10-17 1980-10-17 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14545780A JPS5768916A (en) 1980-10-17 1980-10-17 Delay circuit

Publications (1)

Publication Number Publication Date
JPS5768916A true JPS5768916A (en) 1982-04-27

Family

ID=15385666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14545780A Pending JPS5768916A (en) 1980-10-17 1980-10-17 Delay circuit

Country Status (1)

Country Link
JP (1) JPS5768916A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005104364A1 (en) * 2004-04-19 2005-11-03 Matsushita Electric Industrial Co., Ltd. Group delay adjustment circuit, group delay adjustment system, and group delay adjustment method
JP2012110031A (en) * 2005-08-23 2012-06-07 Quellan Llc Method and system for signal emulation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917649A (en) * 1972-06-05 1974-02-16
JPS4931230A (en) * 1972-07-20 1974-03-20

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917649A (en) * 1972-06-05 1974-02-16
JPS4931230A (en) * 1972-07-20 1974-03-20

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005104364A1 (en) * 2004-04-19 2005-11-03 Matsushita Electric Industrial Co., Ltd. Group delay adjustment circuit, group delay adjustment system, and group delay adjustment method
JP2012110031A (en) * 2005-08-23 2012-06-07 Quellan Llc Method and system for signal emulation

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