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JPS5755447A - Data converting circuit - Google Patents

Data converting circuit

Info

Publication number
JPS5755447A
JPS5755447A JP55131278A JP13127880A JPS5755447A JP S5755447 A JPS5755447 A JP S5755447A JP 55131278 A JP55131278 A JP 55131278A JP 13127880 A JP13127880 A JP 13127880A JP S5755447 A JPS5755447 A JP S5755447A
Authority
JP
Japan
Prior art keywords
write
signals
data
signal
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55131278A
Other languages
Japanese (ja)
Other versions
JPS6252330B2 (en
Inventor
Haruyasu Ito
Akisuke Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55131278A priority Critical patent/JPS5755447A/en
Publication of JPS5755447A publication Critical patent/JPS5755447A/en
Publication of JPS6252330B2 publication Critical patent/JPS6252330B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To speed up the conversion speed from fixed decimal point data to a floating point data and to reduce the software, by making the hardware for the discrimination of positive and negative signs of a fixed decimal point data. CONSTITUTION:Registers 20-50 input write-in data signals 201-501, and input a read/write control signal 80 in common and further decoding control signals 202- 502, and output readout data signals 203-503. The registers 20-50 write in write- in data signals 201-501 when the control signal 80 is at logical 0 and the decoding signals 202-502 are at logical 1, and read out the readout data signals 203-503 when the control signal 80 is at logical 1. The most significant bit signal DW7 of a write-in data signal 401 is inputted to an one input terminal 601 of an inversion circuit 60, another input terminal 602 is connected to a power supply Vcc through a resistor 604 and fixed to ligical 1, then it is given on an output terminal 603 through inversion, and this inversion signal 603 is inputted to the most significant bit 4017.
JP55131278A 1980-09-20 1980-09-20 Data converting circuit Granted JPS5755447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55131278A JPS5755447A (en) 1980-09-20 1980-09-20 Data converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55131278A JPS5755447A (en) 1980-09-20 1980-09-20 Data converting circuit

Publications (2)

Publication Number Publication Date
JPS5755447A true JPS5755447A (en) 1982-04-02
JPS6252330B2 JPS6252330B2 (en) 1987-11-05

Family

ID=15054192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55131278A Granted JPS5755447A (en) 1980-09-20 1980-09-20 Data converting circuit

Country Status (1)

Country Link
JP (1) JPS5755447A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5924342A (en) * 1982-07-30 1984-02-08 Hitachi Ltd Arithmetic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5924342A (en) * 1982-07-30 1984-02-08 Hitachi Ltd Arithmetic device
JPH0425577B2 (en) * 1982-07-30 1992-05-01 Hitachi Ltd

Also Published As

Publication number Publication date
JPS6252330B2 (en) 1987-11-05

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