JPS5752943A - Decoder - Google Patents
DecoderInfo
- Publication number
- JPS5752943A JPS5752943A JP55126898A JP12689880A JPS5752943A JP S5752943 A JPS5752943 A JP S5752943A JP 55126898 A JP55126898 A JP 55126898A JP 12689880 A JP12689880 A JP 12689880A JP S5752943 A JPS5752943 A JP S5752943A
- Authority
- JP
- Japan
- Prior art keywords
- logic
- bits
- signals
- decoders
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used
- H03M7/005—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used using semiconductor devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Executing Machine-Instructions (AREA)
- Logic Circuits (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
PURPOSE:To contrive improvement of integrity, by decoding higher and lower bits of input signals with NAND circuits and by performing decoding of input signal patterns by selecting either the enhancement type MOS or depression type MOS. CONSTITUTION:This decoder is configured in such ways that the higher and lower four bits of an input signal of eight bits are decoded into inversion signals and non- inversion signals by one bit decoders 301 and 401, and transistor groups 302 and 402 composed of enhancement type MOSs E and depression type MOSs D are selectively turned on by the decoded signals. Therefore, the signal Hi which is the output of higher decoders 30 is input into the gate of a transistor 405 of lower decoders 40 after the logic ''0'' of an output line 304 is activated into a logic ''1'' by an invertor 306, and a decode signal Sj is obtained by activating the logic ''0'' of another output line 404 obtained together with the ON condition of the transistor group 402 into a logic ''1'' through another invertor 407.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55126898A JPS5752943A (en) | 1980-09-12 | 1980-09-12 | Decoder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55126898A JPS5752943A (en) | 1980-09-12 | 1980-09-12 | Decoder |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5752943A true JPS5752943A (en) | 1982-03-29 |
JPS636171B2 JPS636171B2 (en) | 1988-02-08 |
Family
ID=14946601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55126898A Granted JPS5752943A (en) | 1980-09-12 | 1980-09-12 | Decoder |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5752943A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5230388A (en) * | 1975-09-04 | 1977-03-08 | Hitachi Ltd | Semiconductor integrated circuit device constructed with insulating ga te field effect transistor |
-
1980
- 1980-09-12 JP JP55126898A patent/JPS5752943A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5230388A (en) * | 1975-09-04 | 1977-03-08 | Hitachi Ltd | Semiconductor integrated circuit device constructed with insulating ga te field effect transistor |
Also Published As
Publication number | Publication date |
---|---|
JPS636171B2 (en) | 1988-02-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE68914322D1 (en) | Dynamic feedback device for an obfuscation key generator. | |
NO981532L (en) | Method and apparatus for encoding audio signals | |
KR920702121A (en) | Encoding / Decoding Devices and Their Communication Networks | |
KR890007504A (en) | Logic operation circuit | |
KR880011794A (en) | Dynamic Decoder Circuit | |
SE9700125L (en) | Encoder and decoder | |
EP0115327A3 (en) | Cmi-decoder | |
JPS5752943A (en) | Decoder | |
JPS6447130A (en) | Bipmos decoder | |
JPS56140595A (en) | Multilevel rom | |
JPS5515598A (en) | Decoding method and decoder for multi-bit digital signal | |
JPS56159897A (en) | Read-only memory | |
JPS5639685A (en) | Decoding system | |
JPS6452285A (en) | Decoder circuit | |
DE69512814D1 (en) | Logic circuit with a programmable logic field for synchronous coding of double words | |
JPS648723A (en) | Logic device | |
ES318469A1 (en) | Binary to multilevel conversion by combining redundant information signal with transition encoded information signal | |
JPS6449429A (en) | Runlength code receiver | |
KR890017703A (en) | I / O line segmentation method by decoding | |
JPS56147236A (en) | Adding circuit | |
JPH05307889A (en) | Encoding circuit | |
JPS5679529A (en) | Logic circuit | |
JPS5355950A (en) | Logical gate circuit | |
GB957643A (en) | Signal decoding apparatus | |
JPS6478024A (en) | Majority decision device |