JPS5750157A - Frequency shift modulator - Google Patents
Frequency shift modulatorInfo
- Publication number
- JPS5750157A JPS5750157A JP12582580A JP12582580A JPS5750157A JP S5750157 A JPS5750157 A JP S5750157A JP 12582580 A JP12582580 A JP 12582580A JP 12582580 A JP12582580 A JP 12582580A JP S5750157 A JPS5750157 A JP S5750157A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input terminal
- terminal
- output
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2003—Modulator circuits; Transmitter circuits for continuous phase modulation
- H04L27/2021—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change per symbol period is not constrained
- H04L27/2025—Modulator circuits; Transmitter circuits for continuous phase modulation in which the phase change per symbol period is not constrained in which the phase changes in a piecewise linear manner within each symbol period
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To enable to apply a digital modulating signal of asynchronism and to avoid phase shift at frequency shift with a simple constitution. CONSTITUTION:An output terminal Q1 of a shift register 2 is connected to a modulation output terminal 10 via a low pass filter 8, and output terminals Qn-1, Qn are connected to a logical circuit 12. The circuit 12 consists of an inverting input AND circuit 14, AND circuit 16 and OR circuit 18, and the output of an circuit 14 and the AND circuit 16 is connected to the input of the OR circuit 18. One input terminal 20 of the inverting input AND circuit 14 is connected to the output terminal Qn-1 of the shift register 2, and another input terminal 22 is connected to a modulation signal input terminal 24 where a digital modulation signal 21 is applied. One input terminal of the AND circuit 16 is an inverting input terminal 28, this terminal is connected to the output terminal Qn of the shift register 2, and another input terminal 26 is connected to the modulation input terminal 24. The output of the OR circuit 18 is connected to a data input terminal 30 of the shift register 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12582580A JPS6053976B2 (en) | 1980-09-10 | 1980-09-10 | frequency shift modulator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12582580A JPS6053976B2 (en) | 1980-09-10 | 1980-09-10 | frequency shift modulator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5750157A true JPS5750157A (en) | 1982-03-24 |
JPS6053976B2 JPS6053976B2 (en) | 1985-11-28 |
Family
ID=14919866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12582580A Expired JPS6053976B2 (en) | 1980-09-10 | 1980-09-10 | frequency shift modulator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6053976B2 (en) |
-
1980
- 1980-09-10 JP JP12582580A patent/JPS6053976B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6053976B2 (en) | 1985-11-28 |
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