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JPS5742249A - Digital transmission system - Google Patents

Digital transmission system

Info

Publication number
JPS5742249A
JPS5742249A JP55117003A JP11700380A JPS5742249A JP S5742249 A JPS5742249 A JP S5742249A JP 55117003 A JP55117003 A JP 55117003A JP 11700380 A JP11700380 A JP 11700380A JP S5742249 A JPS5742249 A JP S5742249A
Authority
JP
Japan
Prior art keywords
data train
outputted
train
output
polarity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55117003A
Other languages
Japanese (ja)
Other versions
JPS5947504B2 (en
Inventor
Hiroshi Kodera
Hideo Hashimoto
Hiroshi Yasuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55117003A priority Critical patent/JPS5947504B2/en
Publication of JPS5742249A publication Critical patent/JPS5742249A/en
Publication of JPS5947504B2 publication Critical patent/JPS5947504B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To reduce the effect of DC interruption at transmission line to pulse train, by controlling the polarity of one code through the use of a time slot immediately before the frame synchronizing location, in a system using bipolar code. CONSTITUTION:When a data train is inputted from a data train input terminal 21, an AND logic between the output of a T flip-flop 24 and that of a counter 26 is taken and 1 is outputted at the position inserted with a polarity controlling pulse. It is taken for OR logic with the data train inputted at an OR gate 22, the output is converted into a bipolar train at a bipolar violation generator 27 and outputted from an output terminal 29. The input data train inputted from an input terminal 31 is converted into a monopolar signal and frame pulses are outputted for every synchronizing location and 0 is outputted for every polarity controlling pulse location from an NOR logical gate 34. The polarity control pulse can be eliminated from the data train by taking AND logic between the data train and the output of the NOR logical gate 34.
JP55117003A 1980-08-27 1980-08-27 Digital transmission method Expired JPS5947504B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55117003A JPS5947504B2 (en) 1980-08-27 1980-08-27 Digital transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55117003A JPS5947504B2 (en) 1980-08-27 1980-08-27 Digital transmission method

Publications (2)

Publication Number Publication Date
JPS5742249A true JPS5742249A (en) 1982-03-09
JPS5947504B2 JPS5947504B2 (en) 1984-11-19

Family

ID=14701049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55117003A Expired JPS5947504B2 (en) 1980-08-27 1980-08-27 Digital transmission method

Country Status (1)

Country Link
JP (1) JPS5947504B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59125144A (en) * 1982-12-30 1984-07-19 ソニー株式会社 Digital signal transmitting system
JPS6444651A (en) * 1987-08-13 1989-02-17 Matsushita Electric Works Ltd Home bus system
EP0319216A2 (en) * 1987-12-01 1989-06-07 Matsushita Electric Industrial Co., Ltd. Coding apparatus and magnetic recording system the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59125144A (en) * 1982-12-30 1984-07-19 ソニー株式会社 Digital signal transmitting system
JPH0522424B2 (en) * 1982-12-30 1993-03-29 Sonii Kk
JPS6444651A (en) * 1987-08-13 1989-02-17 Matsushita Electric Works Ltd Home bus system
JP2511469B2 (en) * 1987-08-13 1996-06-26 松下電工株式会社 Home bus system
EP0319216A2 (en) * 1987-12-01 1989-06-07 Matsushita Electric Industrial Co., Ltd. Coding apparatus and magnetic recording system the same
US5130862A (en) * 1987-12-01 1992-07-14 Matsushita Electric Industrial Co., Ltd. Coding apparatus for converting digital signals into ternary signals whose dc component is equal to zero

Also Published As

Publication number Publication date
JPS5947504B2 (en) 1984-11-19

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