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JPS5741754A - System synchronizing system - Google Patents

System synchronizing system

Info

Publication number
JPS5741754A
JPS5741754A JP11596680A JP11596680A JPS5741754A JP S5741754 A JPS5741754 A JP S5741754A JP 11596680 A JP11596680 A JP 11596680A JP 11596680 A JP11596680 A JP 11596680A JP S5741754 A JPS5741754 A JP S5741754A
Authority
JP
Japan
Prior art keywords
synchronous
circuit
request
reply
synchronous process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11596680A
Other languages
Japanese (ja)
Other versions
JPS5840215B2 (en
Inventor
Kazuo Hibi
Kenichi Shiozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11596680A priority Critical patent/JPS5840215B2/en
Publication of JPS5741754A publication Critical patent/JPS5741754A/en
Publication of JPS5840215B2 publication Critical patent/JPS5840215B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent the occurrence of a deadlock, by installing a sequence deciding circuit within an arithmetic processor having the highest priority and at the same time providing a synchronous process request line and a synchronous reply line independently. CONSTITUTION:A sequence deciding circuit 5 is provided to an arithmetic device BPU1 having the highest priority, and synchronous reply lines 201-212 are provided independently from synchronous process request lines 101-111 as the synchronous interface lines. The circuit 5 decides the accepting sequence of the request according to the priority when the synchronous process request is given from the BPU. On the other hand, BPU2-4 deliver first the synchronous process request to the circuit 5 when the synchronous process is required, delivers the synchronous request to all other BPUs when receiving the synchronous reply from the circuit 5 and starts the synchronous process when receiving the synchronous reply. As a result, the system is prevented from the occurrence of deadlock.
JP11596680A 1980-08-25 1980-08-25 System synchronization method Expired JPS5840215B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11596680A JPS5840215B2 (en) 1980-08-25 1980-08-25 System synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11596680A JPS5840215B2 (en) 1980-08-25 1980-08-25 System synchronization method

Publications (2)

Publication Number Publication Date
JPS5741754A true JPS5741754A (en) 1982-03-09
JPS5840215B2 JPS5840215B2 (en) 1983-09-03

Family

ID=14675539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11596680A Expired JPS5840215B2 (en) 1980-08-25 1980-08-25 System synchronization method

Country Status (1)

Country Link
JP (1) JPS5840215B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538056A (en) * 1982-08-27 1985-08-27 Figgie International, Inc. Card reader for time and attendance
JPS6134693A (en) * 1984-07-27 1986-02-18 ニツタン株式会社 Fire alarm
US4816658A (en) * 1983-01-10 1989-03-28 Casi-Rusco, Inc. Card reader for security system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59203618A (en) * 1983-05-02 1984-11-17 ウクラインスキ−，インスチツ−ト，インジエネロフ，ボドノボ，ホジアイストワ Magnetic separator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538056A (en) * 1982-08-27 1985-08-27 Figgie International, Inc. Card reader for time and attendance
US4816658A (en) * 1983-01-10 1989-03-28 Casi-Rusco, Inc. Card reader for security system
JPS6134693A (en) * 1984-07-27 1986-02-18 ニツタン株式会社 Fire alarm
JPH0370278B2 (en) * 1984-07-27 1991-11-07 Nittan Co Ltd

Also Published As

Publication number Publication date
JPS5840215B2 (en) 1983-09-03

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