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JPS574147A - Semiconductor device and its manufacturing process - Google Patents

Semiconductor device and its manufacturing process

Info

Publication number
JPS574147A
JPS574147A JP7800180A JP7800180A JPS574147A JP S574147 A JPS574147 A JP S574147A JP 7800180 A JP7800180 A JP 7800180A JP 7800180 A JP7800180 A JP 7800180A JP S574147 A JPS574147 A JP S574147A
Authority
JP
Japan
Prior art keywords
metalization layer
wall member
substrate plate
parasitic
brazed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7800180A
Other languages
Japanese (ja)
Other versions
JPS618581B2 (en
Inventor
Shinzo Anazawa
Hideaki Kozu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7800180A priority Critical patent/JPS574147A/en
Publication of JPS574147A publication Critical patent/JPS574147A/en
Publication of JPS618581B2 publication Critical patent/JPS618581B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1617—Cavity coating

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To reduce a parasitic inductance and parasitic capacitance of a package of an element for a high frequency such as GaAsFET etc. by a method wherein a conductive layer arranged in a substrate on which an element is mounted and a metalization layer arranged in a concave part in the wall member are electrically connected with each other. CONSTITUTION:Wall member 2 is fixed around a ceramic substrate plate 1, a metallic lid 3 is brazed to a top surface of it and the element 13 is sealed in air-tight. On the upper surface of the substrate plate 1 are formed a source (grounding) metalization layer 10, a gate (input) metalization layer 8 and a drain (output) metalization layer 9 are formed on the upper surface of the substrate plate 1 such that they may be extended up to side surfaces thereof, and the lead terminals 5 and 4 are brazed to the side surfaces. The wall member 2 is made such that the metalization layer 22 is arranged at the inner surface having the ceramic material 20 provided with openings therein, thereafter the opening part 23 is stamped again in such a way as a part 11 of the metalization layer 22 is left in the concave part. Thereby, it is possible to provide such a structure as the source metalization layer 10 is connected to the lid 3, so that the parasitic effect caused by the container may be reduced and at the same time a disturbance of the parasitic effect may be eliminated.
JP7800180A 1980-06-10 1980-06-10 Semiconductor device and its manufacturing process Granted JPS574147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7800180A JPS574147A (en) 1980-06-10 1980-06-10 Semiconductor device and its manufacturing process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7800180A JPS574147A (en) 1980-06-10 1980-06-10 Semiconductor device and its manufacturing process

Publications (2)

Publication Number Publication Date
JPS574147A true JPS574147A (en) 1982-01-09
JPS618581B2 JPS618581B2 (en) 1986-03-15

Family

ID=13649556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7800180A Granted JPS574147A (en) 1980-06-10 1980-06-10 Semiconductor device and its manufacturing process

Country Status (1)

Country Link
JP (1) JPS574147A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365649A (en) * 1986-09-05 1988-03-24 Nec Corp Pickage for semiconductor
EP1278242A2 (en) * 2001-06-27 2003-01-22 Sumitomo Electric Industries, Ltd. Hermetically sealing enclosure for housing photo-semiconductor devices and photo-semiconductor module incorporating the enclosure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03107112A (en) * 1989-09-20 1991-05-07 Tatsuta Electric Wire & Cable Co Ltd Method for connecting different diameter optical fibers and juncture thereof
JP6362740B1 (en) * 2017-07-12 2018-07-25 株式会社Ｗａｒｒａｎｔｅｅ Settlement management server, program, and settlement method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6365649A (en) * 1986-09-05 1988-03-24 Nec Corp Pickage for semiconductor
EP1278242A2 (en) * 2001-06-27 2003-01-22 Sumitomo Electric Industries, Ltd. Hermetically sealing enclosure for housing photo-semiconductor devices and photo-semiconductor module incorporating the enclosure
EP1278242A3 (en) * 2001-06-27 2004-03-17 Sumitomo Electric Industries, Ltd. Hermetically sealing enclosure for housing photo-semiconductor devices and photo-semiconductor module incorporating the enclosure

Also Published As

Publication number Publication date
JPS618581B2 (en) 1986-03-15

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