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JPS5741040A - Interstage coupling method of electronic circuit - Google Patents

Interstage coupling method of electronic circuit

Info

Publication number
JPS5741040A
JPS5741040A JP55115680A JP11568080A JPS5741040A JP S5741040 A JPS5741040 A JP S5741040A JP 55115680 A JP55115680 A JP 55115680A JP 11568080 A JP11568080 A JP 11568080A JP S5741040 A JPS5741040 A JP S5741040A
Authority
JP
Japan
Prior art keywords
gate
capacitor
fet1
signal
charged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55115680A
Other languages
Japanese (ja)
Inventor
Noburo Hashizume
Hideo Yamada
Terue Kataoka
Takeshi Kojima
Kazutaka Tomizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP55115680A priority Critical patent/JPS5741040A/en
Publication of JPS5741040A publication Critical patent/JPS5741040A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To increase an operation speed and to reduce the power consumption, by connecting a capacity element in series to the gate of an FET having a rectifying gate, and applying an output signal of the prestage. CONSTITUTION:When negative signal voltage is applied to a gate 2, an FET1 is turned off, and a capacitor 10 is charged with a current flowing to a rectifying gate of an FET1' through a resistance 5. After that, when the signal of the gate 2 is returned to its original state, the FET1 is turned on, but since there is no discharge path of the capacitor 10, the potential across its capacitor is held at VDD. Subsequently, when a negative signal is applied to the gate 2 once again, since the capacitor 10 is charged already, it is not charged more, and the potential across the capacitor 10 is not varied, therefore, the signal is transferred at a high speed, and the power consumption is also reduced.
JP55115680A 1980-08-22 1980-08-22 Interstage coupling method of electronic circuit Pending JPS5741040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55115680A JPS5741040A (en) 1980-08-22 1980-08-22 Interstage coupling method of electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55115680A JPS5741040A (en) 1980-08-22 1980-08-22 Interstage coupling method of electronic circuit

Publications (1)

Publication Number Publication Date
JPS5741040A true JPS5741040A (en) 1982-03-06

Family

ID=14668611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55115680A Pending JPS5741040A (en) 1980-08-22 1980-08-22 Interstage coupling method of electronic circuit

Country Status (1)

Country Link
JP (1) JPS5741040A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02113719A (en) * 1988-10-24 1990-04-25 Nec Corp Ecl-cmos logic level conversion circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4843060A (en) * 1971-09-30 1973-06-22
JPS5238852A (en) * 1975-09-22 1977-03-25 Seiko Instr & Electronics Ltd Level shift circuit
JPS546760A (en) * 1977-06-17 1979-01-19 Fujitsu Ltd Logic circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4843060A (en) * 1971-09-30 1973-06-22
JPS5238852A (en) * 1975-09-22 1977-03-25 Seiko Instr & Electronics Ltd Level shift circuit
JPS546760A (en) * 1977-06-17 1979-01-19 Fujitsu Ltd Logic circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02113719A (en) * 1988-10-24 1990-04-25 Nec Corp Ecl-cmos logic level conversion circuit

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