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JPS5739363A - Testing device - Google Patents

Testing device

Info

Publication number
JPS5739363A
JPS5739363A JP55114179A JP11417980A JPS5739363A JP S5739363 A JPS5739363 A JP S5739363A JP 55114179 A JP55114179 A JP 55114179A JP 11417980 A JP11417980 A JP 11417980A JP S5739363 A JPS5739363 A JP S5739363A
Authority
JP
Japan
Prior art keywords
connector
test
test board
dut
socket
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55114179A
Other languages
Japanese (ja)
Inventor
Sadaaki Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55114179A priority Critical patent/JPS5739363A/en
Publication of JPS5739363A publication Critical patent/JPS5739363A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316Testing of analog circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To use a device without changing a test program, by setting a time-lag of an electric signal to each device to be tested (DUT) by length of a cable, after encoding it on the test board which is used for connecting with a handling device, in advance. CONSTITUTION:A test board 4 is equipped with an IC socket 6 for installing a DUT, and a wire 7 is used for each part signal of a test station, and the IC socket 6, and a connector 8 is used for reading a code on the test board. A connector 10 is capable of connecting with each part signal of the test station, and is constituted so that the testboard 4 can be replaced easily depending on a kind of the DUT9. In case of connection as shown in the figure, a code of the connector 8 becomes A3 (hexadecimal), and 256 kinds of combination are available. Accordingly, when a time lag is set to 256msec, correction is executed by 1msec each.
JP55114179A 1980-08-20 1980-08-20 Testing device Pending JPS5739363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55114179A JPS5739363A (en) 1980-08-20 1980-08-20 Testing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55114179A JPS5739363A (en) 1980-08-20 1980-08-20 Testing device

Publications (1)

Publication Number Publication Date
JPS5739363A true JPS5739363A (en) 1982-03-04

Family

ID=14631155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55114179A Pending JPS5739363A (en) 1980-08-20 1980-08-20 Testing device

Country Status (1)

Country Link
JP (1) JPS5739363A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0466939B1 (en) * 1990-02-02 1995-12-27 Advantest Corporation Ic testing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0466939B1 (en) * 1990-02-02 1995-12-27 Advantest Corporation Ic testing device

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