JPS573293A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- JPS573293A JPS573293A JP7643280A JP7643280A JPS573293A JP S573293 A JPS573293 A JP S573293A JP 7643280 A JP7643280 A JP 7643280A JP 7643280 A JP7643280 A JP 7643280A JP S573293 A JPS573293 A JP S573293A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- bits
- bit
- series
- delay circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Shift Register Type Memory (AREA)
Abstract
PURPOSE:To obtain a delay circuit wherein monitoring bits operate on all used addresses effectively in a series RAM, by performing delay by prescribed bits by the series RAM and a shift register. CONSTITUTION:Through an address supplying circuit 20 controlled with a clock from a terminal 3, a signal delayed one bit less than the delay extent of one frame of an input signal is outputted from an RAM10 which has a delaying function and whose number of all address is one bit less than the number of bits of one frame of the input signal. This one-bit delay is compensated by a one-bit shift register 30 which is in series to the RAM10 and controlled with the clock from the terminal 3 to obtain required delay for outputs. Therefore, monitoring bits d1... are read out in every different address period and the delay circuit has the monitoring bits which opeate upon all addresses effectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7643280A JPS573293A (en) | 1980-06-06 | 1980-06-06 | Delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7643280A JPS573293A (en) | 1980-06-06 | 1980-06-06 | Delay circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS573293A true JPS573293A (en) | 1982-01-08 |
JPS6132758B2 JPS6132758B2 (en) | 1986-07-29 |
Family
ID=13604986
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7643280A Granted JPS573293A (en) | 1980-06-06 | 1980-06-06 | Delay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS573293A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58133235A (en) * | 1982-02-02 | 1983-08-08 | オムロン株式会社 | Electronic hemomanometer |
JPS6221713U (en) * | 1985-07-25 | 1987-02-09 | ||
JPS63163556A (en) * | 1986-12-24 | 1988-07-07 | Nec Corp | Memory monitoring system |
US5580190A (en) * | 1995-04-13 | 1996-12-03 | Woody Yang | Soil-holding net |
-
1980
- 1980-06-06 JP JP7643280A patent/JPS573293A/en active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58133235A (en) * | 1982-02-02 | 1983-08-08 | オムロン株式会社 | Electronic hemomanometer |
JPH0344767B2 (en) * | 1982-02-02 | 1991-07-09 | Omuron Kk | |
JPS6221713U (en) * | 1985-07-25 | 1987-02-09 | ||
JPS63163556A (en) * | 1986-12-24 | 1988-07-07 | Nec Corp | Memory monitoring system |
US5580190A (en) * | 1995-04-13 | 1996-12-03 | Woody Yang | Soil-holding net |
Also Published As
Publication number | Publication date |
---|---|
JPS6132758B2 (en) | 1986-07-29 |
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