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JPS5727344A - Error processing system - Google Patents

Error processing system

Info

Publication number
JPS5727344A
JPS5727344A JP10153480A JP10153480A JPS5727344A JP S5727344 A JPS5727344 A JP S5727344A JP 10153480 A JP10153480 A JP 10153480A JP 10153480 A JP10153480 A JP 10153480A JP S5727344 A JPS5727344 A JP S5727344A
Authority
JP
Japan
Prior art keywords
error
phase
tag
processing system
error processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10153480A
Other languages
Japanese (ja)
Inventor
Yuji Oinaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10153480A priority Critical patent/JPS5727344A/en
Publication of JPS5727344A publication Critical patent/JPS5727344A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE:To permit retry of an instruction which causes an error despite the generation of the intermittent error detected at the inlet of a pipeline at any point of time. CONSTITUTION:When an error is detected in the instruction and the inlet of a pipeline, a phase A error tag FF 28-A is set by an OR circuit 24, and when a + phase A release goes on, a phase B error tag FF 28-B is set. In this way, the error tag shifts successively to FFs 28-B, 28-C, 28-D, 28-E, 28-F. When the + phase F release goes to a ''1'' while the phase F error tag 28-F is set, an FF 30 is set, and error reporting is carried out.
JP10153480A 1980-07-24 1980-07-24 Error processing system Pending JPS5727344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10153480A JPS5727344A (en) 1980-07-24 1980-07-24 Error processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10153480A JPS5727344A (en) 1980-07-24 1980-07-24 Error processing system

Publications (1)

Publication Number Publication Date
JPS5727344A true JPS5727344A (en) 1982-02-13

Family

ID=14303104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10153480A Pending JPS5727344A (en) 1980-07-24 1980-07-24 Error processing system

Country Status (1)

Country Link
JP (1) JPS5727344A (en)

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