JPS5725052A - Memory control device - Google Patents
Memory control deviceInfo
- Publication number
- JPS5725052A JPS5725052A JP9929080A JP9929080A JPS5725052A JP S5725052 A JPS5725052 A JP S5725052A JP 9929080 A JP9929080 A JP 9929080A JP 9929080 A JP9929080 A JP 9929080A JP S5725052 A JPS5725052 A JP S5725052A
- Authority
- JP
- Japan
- Prior art keywords
- access
- address
- memory
- module
- address information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9929080A JPS5725052A (en) | 1980-07-22 | 1980-07-22 | Memory control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9929080A JPS5725052A (en) | 1980-07-22 | 1980-07-22 | Memory control device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5725052A true JPS5725052A (en) | 1982-02-09 |
JPS617656B2 JPS617656B2 (ja) | 1986-03-07 |
Family
ID=14243506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9929080A Granted JPS5725052A (en) | 1980-07-22 | 1980-07-22 | Memory control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5725052A (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59144966A (ja) * | 1983-02-08 | 1984-08-20 | Nec Corp | デ−タ処理装置 |
JPH0520181A (ja) * | 1991-07-10 | 1993-01-29 | Fujitsu Ltd | 主記憶制御装置 |
JP4796627B2 (ja) * | 2005-07-05 | 2011-10-19 | インテル・コーポレーション | メモリチャネル内の各メモリデバイスの識別およびアクセス |
JP4838844B2 (ja) * | 2005-06-30 | 2011-12-14 | インテル・コーポレーション | 方法、記憶媒体、システムおよびプログラム |
JP4838843B2 (ja) * | 2005-06-30 | 2011-12-14 | インテル・コーポレーション | マイクロタイル方式がイネーブルされたメモリの自動検出 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0233980U (ja) * | 1988-08-29 | 1990-03-05 |
-
1980
- 1980-07-22 JP JP9929080A patent/JPS5725052A/ja active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59144966A (ja) * | 1983-02-08 | 1984-08-20 | Nec Corp | デ−タ処理装置 |
JPH0520181A (ja) * | 1991-07-10 | 1993-01-29 | Fujitsu Ltd | 主記憶制御装置 |
JP4838844B2 (ja) * | 2005-06-30 | 2011-12-14 | インテル・コーポレーション | 方法、記憶媒体、システムおよびプログラム |
JP4838843B2 (ja) * | 2005-06-30 | 2011-12-14 | インテル・コーポレーション | マイクロタイル方式がイネーブルされたメモリの自動検出 |
JP4796627B2 (ja) * | 2005-07-05 | 2011-10-19 | インテル・コーポレーション | メモリチャネル内の各メモリデバイスの識別およびアクセス |
Also Published As
Publication number | Publication date |
---|---|
JPS617656B2 (ja) | 1986-03-07 |
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