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JPS57203277A - Address inverter buffer circuit - Google Patents

Address inverter buffer circuit

Info

Publication number
JPS57203277A
JPS57203277A JP56088994A JP8899481A JPS57203277A JP S57203277 A JPS57203277 A JP S57203277A JP 56088994 A JP56088994 A JP 56088994A JP 8899481 A JP8899481 A JP 8899481A JP S57203277 A JPS57203277 A JP S57203277A
Authority
JP
Japan
Prior art keywords
turned
electric potential
output
floating
circuit output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56088994A
Other languages
Japanese (ja)
Other versions
JPS6223395B2 (en
Inventor
Tetsuo Misaizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56088994A priority Critical patent/JPS57203277A/en
Publication of JPS57203277A publication Critical patent/JPS57203277A/en
Publication of JPS6223395B2 publication Critical patent/JPS6223395B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To improve the trailing characteristics, to prevent a nonselective circuit output from floating and to stabilize the titled circuit by setting a circuit output to the electric potential raised by the threshold voltage of a depression type MOS FET. CONSTITUTION:When a CS terminal and a -CS terminal are changed from high to low electric potential and low to high respectively, transistors (TR) Q1, Q2 and Q3 are turned off, TRs Q14 and Q15 are turned on and a node 4 is turned to low electric potential. In this case, a circuit output which has been an electric power Vcc level in the preceeding cycle is made floating status. If TR Q16 is turned on, the output in the floating status is made to fall and the outputs in the low electric potential are made to rise, so that a complementary output is turned to an intermediate potential between electric power and earth potential. TRs Q17 and Q18 act so that the complementary output is prevented from floating and the circuit output is set to an electric potential raised by the threshold voltage of a depression type MOS FET.
JP56088994A 1981-06-10 1981-06-10 Address inverter buffer circuit Granted JPS57203277A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56088994A JPS57203277A (en) 1981-06-10 1981-06-10 Address inverter buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56088994A JPS57203277A (en) 1981-06-10 1981-06-10 Address inverter buffer circuit

Publications (2)

Publication Number Publication Date
JPS57203277A true JPS57203277A (en) 1982-12-13
JPS6223395B2 JPS6223395B2 (en) 1987-05-22

Family

ID=13958359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56088994A Granted JPS57203277A (en) 1981-06-10 1981-06-10 Address inverter buffer circuit

Country Status (1)

Country Link
JP (1) JPS57203277A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62205596A (en) * 1986-03-05 1987-09-10 Mitsubishi Electric Corp Input buffer circuit for mos type memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142922A (en) * 1975-06-04 1976-12-08 Hitachi Ltd Address buffer amplifier
JPS5641579A (en) * 1979-09-10 1981-04-18 Toshiba Corp Address selector
JPS5671881A (en) * 1979-11-15 1981-06-15 Fujitsu Ltd Decoder circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142922A (en) * 1975-06-04 1976-12-08 Hitachi Ltd Address buffer amplifier
JPS5641579A (en) * 1979-09-10 1981-04-18 Toshiba Corp Address selector
JPS5671881A (en) * 1979-11-15 1981-06-15 Fujitsu Ltd Decoder circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62205596A (en) * 1986-03-05 1987-09-10 Mitsubishi Electric Corp Input buffer circuit for mos type memory device

Also Published As

Publication number Publication date
JPS6223395B2 (en) 1987-05-22

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