JPS5720013A - Digital filter device - Google Patents
Digital filter deviceInfo
- Publication number
- JPS5720013A JPS5720013A JP9446480A JP9446480A JPS5720013A JP S5720013 A JPS5720013 A JP S5720013A JP 9446480 A JP9446480 A JP 9446480A JP 9446480 A JP9446480 A JP 9446480A JP S5720013 A JPS5720013 A JP S5720013A
- Authority
- JP
- Japan
- Prior art keywords
- adder
- circuit
- supplied
- overflow
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003111 delayed effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/04—Recursive filters
- H03H17/0461—Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To prevent the overflow of external equipment by outputting the maximum and minimum values of the dynamic range of arithmetic selectively when an overflow occurs to the dynamic range. CONSTITUTION:A multiplier 1 multiplies input data by K and supplies the result to an adder 2. The utput of the adder is supplied via a digit overflow processing circuit 11 to a delay circuit 3 to be delayed and the output of the circuit 3 is doubled 2 and supplied to an adder 4. The output of the circuit 3 is multiplied 7 by b1 and the result is supplied to an adder 8 and a delay circuit 9. The output of the circuit 9 is supplied to an adder 6 and also supplied to the adder 8 after being multiplied 10 by b2. The adder 8 calculates the difference between the outputs of the multiplier 7 and multipiers 10 and applies it to the adder 2. In this constitution, if an overflow occurs, the circuit 11 operates to output data which is the maximum value of a dynamic range when it is positive and the minimum value when negative. Thus, the overflow is prevented.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9446480A JPS5720013A (en) | 1980-07-09 | 1980-07-09 | Digital filter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9446480A JPS5720013A (en) | 1980-07-09 | 1980-07-09 | Digital filter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5720013A true JPS5720013A (en) | 1982-02-02 |
| JPS6337977B2 JPS6337977B2 (en) | 1988-07-27 |
Family
ID=14110993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9446480A Granted JPS5720013A (en) | 1980-07-09 | 1980-07-09 | Digital filter device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5720013A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6993545B2 (en) | 2000-09-27 | 2006-01-31 | Kabushiki Kaisha Toshiba | Digital filter with protection against overflow oscillation |
-
1980
- 1980-07-09 JP JP9446480A patent/JPS5720013A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6993545B2 (en) | 2000-09-27 | 2006-01-31 | Kabushiki Kaisha Toshiba | Digital filter with protection against overflow oscillation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6337977B2 (en) | 1988-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS567172A (en) | Method and device of complex ternary correlation for adaptive gradient calculation | |
| JPS56147260A (en) | Lsi for digital signal processing | |
| JPS5720013A (en) | Digital filter device | |
| KR920020840A (en) | Circulating Digital Filter | |
| JPS5526750A (en) | Digital filter | |
| JPS5720014A (en) | Digit overflow processor of digital filter | |
| JPS56149823A (en) | Band pass filter | |
| JPS5360539A (en) | Digital filter | |
| JPS5663649A (en) | Parallel multiplication apparatus | |
| JPS53138667A (en) | A/d converter circuit | |
| JPS5724113A (en) | Digital filter device | |
| JPS5642869A (en) | Motion picture/still picture separator | |
| KR0170339B1 (en) | Digital integrator | |
| JPS5448471A (en) | Coding system | |
| JPS647809A (en) | Digital filter | |
| JPS5422140A (en) | Digital differential analyzer | |
| JPS5453848A (en) | Delay circuit of digital filter | |
| KR940007927B1 (en) | Multiplication circuit of digital filter | |
| JPS56120212A (en) | Digital filter of block floating decimal point | |
| JPS6461121A (en) | Semiconductor integrated circuit | |
| JPS6490608A (en) | Digital filter | |
| KR930000650Y1 (en) | Noise Canceling Circuit of Luminance Signal | |
| JPS6486238A (en) | Subtracter | |
| RU2019026C1 (en) | Ripple filter | |
| JPS57157372A (en) | Operation error correcting method |