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JPS57196339A - Accelerating system of input and output instruction - Google Patents

Accelerating system of input and output instruction

Info

Publication number
JPS57196339A
JPS57196339A JP8081781A JP8081781A JPS57196339A JP S57196339 A JPS57196339 A JP S57196339A JP 8081781 A JP8081781 A JP 8081781A JP 8081781 A JP8081781 A JP 8081781A JP S57196339 A JPS57196339 A JP S57196339A
Authority
JP
Japan
Prior art keywords
channel
storage
ccw
cpu1
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8081781A
Other languages
Japanese (ja)
Other versions
JPS6028023B2 (en
Inventor
Koji Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8081781A priority Critical patent/JPS6028023B2/en
Publication of JPS57196339A publication Critical patent/JPS57196339A/en
Publication of JPS6028023B2 publication Critical patent/JPS6028023B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize a high-speed operation for the input/output instruction, by writing a series of channel programs directly into a control storage through a CPU and executing continuously the channel programs through a channel. CONSTITUTION:A CPU1 stores the loaded channel command word CCW and the channel command address into a control storage 5 via an address bus 3 and a data bus 4 and simultaneously with the load operation. Then the CPU1 sets a channel command word end pointer to the storage 5 when the 1st reading command arrives or the buffer of the storage 5 is filled up. In case the corresponding channel extracts the word CCW out of the storage 5, the channel itself fetches the word CCW from a main storage device 2 for the next and subsequent words CCW after finding out a pointer. In response to the end of the storing action of the storage 5, the CPU1 makes a channel 4a start an early release input/output start instruction through the storage 5 and at the same time sets a proper condition to complete an instruction.
JP8081781A 1981-05-29 1981-05-29 I/O instruction acceleration method Expired JPS6028023B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8081781A JPS6028023B2 (en) 1981-05-29 1981-05-29 I/O instruction acceleration method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8081781A JPS6028023B2 (en) 1981-05-29 1981-05-29 I/O instruction acceleration method

Publications (2)

Publication Number Publication Date
JPS57196339A true JPS57196339A (en) 1982-12-02
JPS6028023B2 JPS6028023B2 (en) 1985-07-02

Family

ID=13728997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8081781A Expired JPS6028023B2 (en) 1981-05-29 1981-05-29 I/O instruction acceleration method

Country Status (1)

Country Link
JP (1) JPS6028023B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121526A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Information processing system input/output startup processing method
JPS62260263A (en) * 1986-05-07 1987-11-12 Fujitsu Ltd Program control method using multiprocessor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121526A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Information processing system input/output startup processing method
JPS62260263A (en) * 1986-05-07 1987-11-12 Fujitsu Ltd Program control method using multiprocessor

Also Published As

Publication number Publication date
JPS6028023B2 (en) 1985-07-02

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