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JPS57192177A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPS57192177A
JPS57192177A JP56076664A JP7666481A JPS57192177A JP S57192177 A JPS57192177 A JP S57192177A JP 56076664 A JP56076664 A JP 56076664A JP 7666481 A JP7666481 A JP 7666481A JP S57192177 A JPS57192177 A JP S57192177A
Authority
JP
Japan
Prior art keywords
frame
cap
package
solid
image pickup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56076664A
Other languages
Japanese (ja)
Inventor
Yoshio Iwata
Tsutomu Fujita
Kiyoshi Tanaka
Atsuki Furunaga
Hiroshi Kosemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56076664A priority Critical patent/JPS57192177A/en
Publication of JPS57192177A publication Critical patent/JPS57192177A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To make air-tight sealing with high reliability, by inserting a solder member made of a low melting point metal between a metal frame of a cap and that at the package upper stage. CONSTITUTION:A package 1 made of ceramic has a cap 10 made of a transparent glass plate 7 and a ceramic frame and metal frame 9 to prevent degradation of a contained photodetector 5 for the front side. An An/Sn solder member 12 is melt-fixed with local heating and fixed between the frame 9 of the cap 10 and a metallic frame 11 formed at the upper stage of the package 1 for air- tight sealing.
JP56076664A 1981-05-22 1981-05-22 Solid-state image pickup device Pending JPS57192177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076664A JPS57192177A (en) 1981-05-22 1981-05-22 Solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076664A JPS57192177A (en) 1981-05-22 1981-05-22 Solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPS57192177A true JPS57192177A (en) 1982-11-26

Family

ID=13611672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076664A Pending JPS57192177A (en) 1981-05-22 1981-05-22 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPS57192177A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5465675A (en) * 1977-11-04 1979-05-26 Toray Industries Sack for packing wool
JPS54146985A (en) * 1978-05-10 1979-11-16 Hitachi Ltd Package for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5465675A (en) * 1977-11-04 1979-05-26 Toray Industries Sack for packing wool
JPS54146985A (en) * 1978-05-10 1979-11-16 Hitachi Ltd Package for semiconductor device

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