[go: up one dir, main page]

JPS57189391A - Nonvolatile semiconductor memory integrated circuit - Google Patents

Nonvolatile semiconductor memory integrated circuit

Info

Publication number
JPS57189391A
JPS57189391A JP7324681A JP7324681A JPS57189391A JP S57189391 A JPS57189391 A JP S57189391A JP 7324681 A JP7324681 A JP 7324681A JP 7324681 A JP7324681 A JP 7324681A JP S57189391 A JPS57189391 A JP S57189391A
Authority
JP
Japan
Prior art keywords
region
electrode
voltage
substrate
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7324681A
Other languages
Japanese (ja)
Other versions
JPH0370879B2 (en
Inventor
Yutaka Hayashi
Yoshikazu Kojima
Masaaki Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology, Seiko Instruments Inc filed Critical Agency of Industrial Science and Technology
Priority to JP7324681A priority Critical patent/JPS57189391A/en
Publication of JPS57189391A publication Critical patent/JPS57189391A/en
Publication of JPH0370879B2 publication Critical patent/JPH0370879B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To realize low program voltages without degrading holding characteristics by applying a constant voltage smaller than source voltage upon program electrodes serving also as read output electrodes. CONSTITUTION:When a reverse bias (write) voltage is applied to a control gate area 37 of n type capacitive-coupled strongly via an insulation film 38 to a floating gate electrode 35 in the case of a p type substrate 31, the surface of the substrate 31 under the film 48 depletes or inverts. Further, when a forward current is injected to the substrate 31 from an electron injector region 36 of n type as shown by an arrow D, part of said current enters the electrode 35. To erase this, a thin insulation film region 45 is provided between the electrode 35 and a drain region 33, and when a positive voltage (erasing voltage) is applied to the region 37, a tunnel current flows in the film 45, and the electrons in the electrode 35 flows out into the region 33. To read out, a constant voltage (source voltage) is applied to the region 37, and the read out is accomplished by the current between the source and drain regions flowing dependently upon the electron density in the electrode 35.
JP7324681A 1981-05-15 1981-05-15 Nonvolatile semiconductor memory integrated circuit Granted JPS57189391A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7324681A JPS57189391A (en) 1981-05-15 1981-05-15 Nonvolatile semiconductor memory integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7324681A JPS57189391A (en) 1981-05-15 1981-05-15 Nonvolatile semiconductor memory integrated circuit

Publications (2)

Publication Number Publication Date
JPS57189391A true JPS57189391A (en) 1982-11-20
JPH0370879B2 JPH0370879B2 (en) 1991-11-11

Family

ID=13512628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7324681A Granted JPS57189391A (en) 1981-05-15 1981-05-15 Nonvolatile semiconductor memory integrated circuit

Country Status (1)

Country Link
JP (1) JPS57189391A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045999A (en) * 1983-08-24 1985-03-12 Hitachi Ltd Semiconductor non-volatile storage device
WO1996026521A1 (en) * 1995-02-22 1996-08-29 National Semiconductor Corporation A method for programming a single eprom or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5536937A (en) * 1978-09-04 1980-03-14 Nec Corp Nonvolatile semiconductor storage unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5536937A (en) * 1978-09-04 1980-03-14 Nec Corp Nonvolatile semiconductor storage unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045999A (en) * 1983-08-24 1985-03-12 Hitachi Ltd Semiconductor non-volatile storage device
WO1996026521A1 (en) * 1995-02-22 1996-08-29 National Semiconductor Corporation A method for programming a single eprom or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction

Also Published As

Publication number Publication date
JPH0370879B2 (en) 1991-11-11

Similar Documents

Publication Publication Date Title
US5341342A (en) Flash memory cell structure
US4616340A (en) Non-volatile semiconductor memory
US4821236A (en) Semiconductor nonvolatile memory
EP0218342A2 (en) Memory cells for integrated circuits
US5790460A (en) Method of erasing a flash EEPROM memory
JPH07120720B2 (en) Nonvolatile semiconductor memory device
US4794433A (en) Non-volatile semiconductor memory with non-uniform gate insulator
JPH06302828A (en) Nonvolatile semiconductor memory device
JPS57141969A (en) Nonvolatile semiconductor memory
KR920001402B1 (en) Nonvolatile Semiconductor Memory
JPS6322626B2 (en)
JPS57189391A (en) Nonvolatile semiconductor memory integrated circuit
GB1517927A (en) N-channel field storage transistors
JPH01212472A (en) Nonvolatile semiconductor storage device
KR980006399A (en) Erasing Method of Nonvolatile Semiconductor Memory Device
KR960011187B1 (en) Non-volatile semiconductor memory using a thin film transistor
US5930171A (en) Constant-current source with an EEPROM cell
JP2867267B2 (en) Semiconductor nonvolatile memory and operation method thereof
JPH0352268A (en) Writing and reading method for semiconductor nonvolatile memory
JPS57180182A (en) Semiconductor involatile memory device
JPH0451072B2 (en)
JPS644077A (en) Memory cell
JPS62229982A (en) Semiconductor memory
JPH03153087A (en) Semiconductor storage device
Mizutani et al. Characteristics of a new EPROM cell structure with a sidewall floating gate