JPS57186350A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an IC device proper to a master sliced LSI by bringing a section between arbitrary adjacent cell rows near more than sections between other cell rows and forming a plurality of wiring onto the section between the cell rows in the direction that the longitudinal direction crosses at right angles with the cell rows through an insulating layer. CONSTITUTION:Series two-throw P type and N type channel FETs 421, 422 are oppositely arranged to one main surface of a LSI chip 41, and the sections 44 among the odd number cell rows are made narrower than the even number cell rows. The FETs 421 have a pair of gate electrodes 4212 on the insulating film 51 on sections among P layers 4211 and the FETs 422 a pair of gate electrodes 4222 on the insulating film 51 on sections among N layers 4221, and the wiring 46, the longitudinal direction thereof crosses at right angles with the cell rows, is also formed onto the sections 44 among the cell rows by poly Si through the insulating film 51. The surface is coated with an insulating film 52, holes 47 are bored, power supply wires 48 and grounding wires 49 are mounted, the Al wiring 56, the longitudinal direction thereof crosses at right angles with the cell rows, is formed through an insulating film 53, and the surface is coated with an insulating film 54. The rate of wiring is improved and this constitution is advantageous for automatic connection because wires can be connected in the direction of the cell rows by wiring 55 and in the direction rectangular to the rows by the wiring 46 and the wiring 56 can be used for connection among logic blocks.