JPS57186292A - Insulating gate type field effect semiconductor device - Google Patents
Insulating gate type field effect semiconductor deviceInfo
- Publication number
- JPS57186292A JPS57186292A JP7165281A JP7165281A JPS57186292A JP S57186292 A JPS57186292 A JP S57186292A JP 7165281 A JP7165281 A JP 7165281A JP 7165281 A JP7165281 A JP 7165281A JP S57186292 A JPS57186292 A JP S57186292A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- semiconductor substrate
- gate insulating
- semiconductor device
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To eliminate an erroneous writing caused by the floating effect of a non-selective memory cell, by installing functioning section which impresses an electric potential having a polarity which inhibits formation of an inversed layer in the semiconductor substrate below the gate insulating film upon the gate electrode. CONSTITUTION:A source area 2 and a drain area 3 are formed in a semiconductor substrate 1. Moreover, a floating gate 5 is formed in gate insulating substances 41 and 42 and a control gate 6 is formed on the insulating substance. Then, a functioning section which impresses an electric potential of a polarity which inhibits formation of an inversed layer on the surface of the semiconductor substrate 1 below the gate insulating film 4 upon a gate electrode 6, is added to such a configuration. Thereafter, it is arranged so as to prevent the floating effect of the non-selective memory cell in a memory matrix 11, by installing, for example, a digit line buffer circuit 12 having a voltage controlling function and a word line buffer circuit 13 in the periphery of the memory matrix 11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7165281A JPS57186292A (en) | 1981-05-12 | 1981-05-12 | Insulating gate type field effect semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7165281A JPS57186292A (en) | 1981-05-12 | 1981-05-12 | Insulating gate type field effect semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57186292A true JPS57186292A (en) | 1982-11-16 |
JPS6122400B2 JPS6122400B2 (en) | 1986-05-31 |
Family
ID=13466748
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7165281A Granted JPS57186292A (en) | 1981-05-12 | 1981-05-12 | Insulating gate type field effect semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57186292A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5542307A (en) * | 1978-09-14 | 1980-03-25 | Toshiba Corp | Semiconductor memory unit |
GB2053611A (en) * | 1979-07-02 | 1981-02-04 | Mostek Corp | Programmable read only memory integrated circuit with bit-check and de-programming modes and methods for programming and testing said circuit |
-
1981
- 1981-05-12 JP JP7165281A patent/JPS57186292A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5542307A (en) * | 1978-09-14 | 1980-03-25 | Toshiba Corp | Semiconductor memory unit |
GB2053611A (en) * | 1979-07-02 | 1981-02-04 | Mostek Corp | Programmable read only memory integrated circuit with bit-check and de-programming modes and methods for programming and testing said circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6122400B2 (en) | 1986-05-31 |
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