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JPS57181137A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57181137A
JPS57181137A JP56066476A JP6647681A JPS57181137A JP S57181137 A JPS57181137 A JP S57181137A JP 56066476 A JP56066476 A JP 56066476A JP 6647681 A JP6647681 A JP 6647681A JP S57181137 A JPS57181137 A JP S57181137A
Authority
JP
Japan
Prior art keywords
film
insulation layer
layer
element separation
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56066476A
Other languages
Japanese (ja)
Inventor
Satoru Maeda
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56066476A priority Critical patent/JPS57181137A/en
Priority to US06/307,877 priority patent/US4560421A/en
Publication of JPS57181137A publication Critical patent/JPS57181137A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To realize an element separation region divided finely in a simple process, by implanting ions through a selective etching film and an insulation film underneath, and forming a reverse protection layer and an element region opening mask simultaneously. CONSTITUTION:Ions of boron are implanted in a near boundary under an insulation layer 12 masked by a resist pattern 14 on the insulation layer 12 and an Al film 13 formed on a semiconductor substrate 11. The Al film 13 has etching selectivity, and at the sane time, a reverse protection layer 15 is formed. Next, a mask 14 and the film 13 underneath are removed by etching. The insulation layer 12, masked by a remaining Al film 13', is etched. An element region is exposed around an element separation layer 16 consisting of insulation layer. Electrodes of source 19, drain 20 and gate 18 are formed afterwards by a conventional method. This attains high integration by forming a refined element separation region with no bird beak in a simplified process.
JP56066476A 1980-10-02 1981-05-01 Manufacture of semiconductor device Pending JPS57181137A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56066476A JPS57181137A (en) 1981-05-01 1981-05-01 Manufacture of semiconductor device
US06/307,877 US4560421A (en) 1980-10-02 1981-10-02 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56066476A JPS57181137A (en) 1981-05-01 1981-05-01 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57181137A true JPS57181137A (en) 1982-11-08

Family

ID=13316865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56066476A Pending JPS57181137A (en) 1980-10-02 1981-05-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57181137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008141148A (en) * 2006-12-04 2008-06-19 Hynix Semiconductor Inc Method of forming oxide film pattern and patterning method for semiconductor element using it

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008141148A (en) * 2006-12-04 2008-06-19 Hynix Semiconductor Inc Method of forming oxide film pattern and patterning method for semiconductor element using it

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