JPS57167660A - Forming method for high-melting point metallic silicide layer - Google Patents
Forming method for high-melting point metallic silicide layerInfo
- Publication number
- JPS57167660A JPS57167660A JP4710481A JP4710481A JPS57167660A JP S57167660 A JPS57167660 A JP S57167660A JP 4710481 A JP4710481 A JP 4710481A JP 4710481 A JP4710481 A JP 4710481A JP S57167660 A JPS57167660 A JP S57167660A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- layer
- melting point
- onto
- polycrystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002844 melting Methods 0.000 title abstract 4
- 229910021332 silicide Inorganic materials 0.000 title abstract 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title abstract 3
- 238000000034 method Methods 0.000 title 1
- 239000002184 metal Substances 0.000 abstract 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract 3
- 239000011574 phosphorus Substances 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 2
- -1 Phosphorus ions Chemical class 0.000 abstract 1
- 238000005275 alloying Methods 0.000 abstract 1
- 238000000137 annealing Methods 0.000 abstract 1
- 230000003028 elevating effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To form the excellent silicide layer having low resistance extending over the whole region by forming a polycrystal Si layer, to which phosphorus is doped, onto a base body to be treated, heating and annealing the base body, shaping a high-melting point metal layer onto the Si layer, elevating the temperature and alloying the Si layer and the metal layer. CONSTITUTION:Field oxide films 2 are formed to the surface of the first conduction type semiconductor substrate 1 and channel cut regions 3 under the films 2. A gate oxide film 4 is shaped onto the surface of the substrate 1, and a polycrystal Si layer 5 not doped is coated and molded. Phosphorus ions 6 are implanted in the whole upper surface of the layer 5, and the substrate 1 is heated and annealed in an inactive atmosphere and the polycrystal Si layers 5' to which phosphorus is doped are formed. The high-melting point metal layers 7 are shaped onto the layers 5', and gate wiring 8 with double structure consisting of the layers 5' and the layers 7 is formed onto the film 4 through selective etching. The whole is heated in an inactive atmosphere or vacuum, the layers 7 and the layers 5' are alloyed, and the gate wiring 9 of high-melting point metallic silicide is shaped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4710481A JPS57167660A (en) | 1981-03-30 | 1981-03-30 | Forming method for high-melting point metallic silicide layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4710481A JPS57167660A (en) | 1981-03-30 | 1981-03-30 | Forming method for high-melting point metallic silicide layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57167660A true JPS57167660A (en) | 1982-10-15 |
| JPS639661B2 JPS639661B2 (en) | 1988-03-01 |
Family
ID=12765863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4710481A Granted JPS57167660A (en) | 1981-03-30 | 1981-03-30 | Forming method for high-melting point metallic silicide layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57167660A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH027517A (en) * | 1988-06-27 | 1990-01-11 | Sony Corp | Manufacture of semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7289194B2 (en) | 2018-12-18 | 2023-06-09 | 住友化学株式会社 | Method for producing porous layer, laminate, separator for non-aqueous electrolyte secondary battery, and non-aqueous electrolyte secondary battery |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333077A (en) * | 1976-09-08 | 1978-03-28 | Nec Corp | Semiconductor integrated circuit |
-
1981
- 1981-03-30 JP JP4710481A patent/JPS57167660A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333077A (en) * | 1976-09-08 | 1978-03-28 | Nec Corp | Semiconductor integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH027517A (en) * | 1988-06-27 | 1990-01-11 | Sony Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS639661B2 (en) | 1988-03-01 |
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