JPS57167196A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS57167196A JPS57167196A JP56051411A JP5141181A JPS57167196A JP S57167196 A JPS57167196 A JP S57167196A JP 56051411 A JP56051411 A JP 56051411A JP 5141181 A JP5141181 A JP 5141181A JP S57167196 A JPS57167196 A JP S57167196A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- signal
- power supply
- circuit
- selection state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Power Sources (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Stand-By Power Supply Arrangements (AREA)
Abstract
PURPOSE:To obtain an IC memory for low voltage, by using a means that shifts to a non-selection state after detecting that the power supply is less than a prescribed level higher than the minimum value of the data holding voltage. CONSTITUTION:A power supply voltage detecting circuit 7 is set within a control circuit part 6, and each block excepting the part 6 is controlled by the internal control signals CS' and W'. The signal CS' is set at a low level when the chip selection signal, i.e., an external control signal is set at a high level. Thus a non- selection state is secured. In other words, when the voltage is dropped, the circuit 7 detects it and produces the detection signal R to set the signals CS' at a low level through an NUR301.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56051411A JPS57167196A (en) | 1981-04-06 | 1981-04-06 | Memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56051411A JPS57167196A (en) | 1981-04-06 | 1981-04-06 | Memory circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57167196A true JPS57167196A (en) | 1982-10-14 |
JPS6160514B2 JPS6160514B2 (en) | 1986-12-20 |
Family
ID=12886184
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56051411A Granted JPS57167196A (en) | 1981-04-06 | 1981-04-06 | Memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57167196A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59117776A (en) * | 1982-12-24 | 1984-07-07 | Hitachi Micro Comput Eng Ltd | Semiconductor storage device |
US4553225A (en) * | 1981-09-26 | 1985-11-12 | Fujitsu Limited | Method of testing IC memories |
-
1981
- 1981-04-06 JP JP56051411A patent/JPS57167196A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4553225A (en) * | 1981-09-26 | 1985-11-12 | Fujitsu Limited | Method of testing IC memories |
JPS59117776A (en) * | 1982-12-24 | 1984-07-07 | Hitachi Micro Comput Eng Ltd | Semiconductor storage device |
Also Published As
Publication number | Publication date |
---|---|
JPS6160514B2 (en) | 1986-12-20 |
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