JPS57163878A - Test signal generating circuit for integrated circuit - Google Patents
Test signal generating circuit for integrated circuitInfo
- Publication number
- JPS57163878A JPS57163878A JP57032470A JP3247082A JPS57163878A JP S57163878 A JPS57163878 A JP S57163878A JP 57032470 A JP57032470 A JP 57032470A JP 3247082 A JP3247082 A JP 3247082A JP S57163878 A JPS57163878 A JP S57163878A
- Authority
- JP
- Japan
- Prior art keywords
- test
- test signal
- levels
- generated
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To evade malfunction due to a noise, etc., to an input terminal by generating a test signal only when a test instruction generated inside an LSI resides while a test mode specified for an input terminal is not used as the test signal as it is. CONSTITUTION:System specification is so determined that both input terminals 1 and 2 have not levels of logic 1 for normal operation. For the specification of a test mode, when the input terminals 1 and 2 are both held at the levels of logic 1 and a strobe signal C is supplied, information showing that signals from the input terminals 1 and 2 are both held at levels 1 is stored in a succeeding latch 7 and a test signal B has a level 1, thus specifying the test mode. In this way, only when the signals from the terminal 1 and 2 both have the levels 1 and a test command C is supplied, the test signal is generated and even if the test command C generated in an LSI erroneously during normal operation, no test signal is generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57032470A JPS57163878A (en) | 1982-03-03 | 1982-03-03 | Test signal generating circuit for integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57032470A JPS57163878A (en) | 1982-03-03 | 1982-03-03 | Test signal generating circuit for integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57163878A true JPS57163878A (en) | 1982-10-08 |
JPH0320710B2 JPH0320710B2 (en) | 1991-03-20 |
Family
ID=12359853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57032470A Granted JPS57163878A (en) | 1982-03-03 | 1982-03-03 | Test signal generating circuit for integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57163878A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6525967B1 (en) | 1995-02-10 | 2003-02-25 | Micron Technology, Inc. | Fast-sensing amplifier for flash memory |
US6578124B1 (en) | 1995-02-10 | 2003-06-10 | Micron Technology, Inc. | Serial command port method, circuit, and system including main and command clock generators to filter signals of less than a predetermined duration |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53121543A (en) * | 1977-03-31 | 1978-10-24 | Toshiba Corp | Check circuit |
-
1982
- 1982-03-03 JP JP57032470A patent/JPS57163878A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53121543A (en) * | 1977-03-31 | 1978-10-24 | Toshiba Corp | Check circuit |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6525967B1 (en) | 1995-02-10 | 2003-02-25 | Micron Technology, Inc. | Fast-sensing amplifier for flash memory |
US6578124B1 (en) | 1995-02-10 | 2003-06-10 | Micron Technology, Inc. | Serial command port method, circuit, and system including main and command clock generators to filter signals of less than a predetermined duration |
US6581146B1 (en) | 1995-02-10 | 2003-06-17 | Micron Technology, Inc. | Serial command port method, circuit, and system including main and command clock generators to filter signals of less than a predetermined duration |
US6744673B2 (en) | 1995-02-10 | 2004-06-01 | Micron Technology, Inc. | Feedback biasing integrated circuit |
US6914822B2 (en) | 1995-02-10 | 2005-07-05 | Micron Technology Inc. | Read-biasing and amplifying system |
US6996010B2 (en) | 1995-02-10 | 2006-02-07 | Micron Technology, Inc. | Fast-sensing amplifier for flash memory |
Also Published As
Publication number | Publication date |
---|---|
JPH0320710B2 (en) | 1991-03-20 |
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