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JPS57162550A - Battery checking system - Google Patents

Battery checking system

Info

Publication number
JPS57162550A
JPS57162550A JP56047411A JP4741181A JPS57162550A JP S57162550 A JPS57162550 A JP S57162550A JP 56047411 A JP56047411 A JP 56047411A JP 4741181 A JP4741181 A JP 4741181A JP S57162550 A JPS57162550 A JP S57162550A
Authority
JP
Japan
Prior art keywords
logic
parity
clock signal
parts
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56047411A
Other languages
Japanese (ja)
Inventor
Toshiki Nakajima
Yasuo Baba
Yasuo Doi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56047411A priority Critical patent/JPS57162550A/en
Publication of JPS57162550A publication Critical patent/JPS57162550A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To detect an error by which a mistake is given to the full bit logic ''0'' or ''1'', by performing an odd parity check based on the clock signal which is produced prior to the transfer of data and then carrying out an even parity check based on the following clock signal. CONSTITUTION:The signals corresponding to logic ''0'' and ''1'' are stored in the parity set bit storing parts 3 and 14 respectively based on the clock signal CL which is used for the transfer of data DATA0-DATA7. For instance, when the logic ''0'' is stored in the parts 3 and 14 each, the logic ''1'' is delivered for the parity bit in a parity producing circuit 11 and to ''10110100'' of the DATA0- DATA7. A parity checking circuit 12 checks the data including a parity bit PB plus the logic ''0'' of the part 14 in the form of a piece of data. After this, the next clock signal CL is applied to the parts 3 and 14 respectively. As a result, the logic ''1'' is stored in the parts 3 and 14 each.
JP56047411A 1981-03-31 1981-03-31 Battery checking system Pending JPS57162550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047411A JPS57162550A (en) 1981-03-31 1981-03-31 Battery checking system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047411A JPS57162550A (en) 1981-03-31 1981-03-31 Battery checking system

Publications (1)

Publication Number Publication Date
JPS57162550A true JPS57162550A (en) 1982-10-06

Family

ID=12774382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047411A Pending JPS57162550A (en) 1981-03-31 1981-03-31 Battery checking system

Country Status (1)

Country Link
JP (1) JPS57162550A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07202850A (en) * 1993-12-28 1995-08-04 Nec Corp Data transmission system by crc protection
US6920604B2 (en) * 2002-04-08 2005-07-19 Galazar Networks, Inc. Systems and methods for high speed serial encoding and decoding for data and control interfaces

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07202850A (en) * 1993-12-28 1995-08-04 Nec Corp Data transmission system by crc protection
US6920604B2 (en) * 2002-04-08 2005-07-19 Galazar Networks, Inc. Systems and methods for high speed serial encoding and decoding for data and control interfaces

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